ADSP-BF538F EZ-KIT Lite Evaluation System Manual 1-9
Using ADSP-BF538F EZ-KIT Lite
SDRAM registers are configured automatically through the debugger each
time the processor is reset. The values in Table 1-2 are used whenever
SDRAM bank 0 is accessed through the debugger (for example, when
viewing memory windows or loading a program). The numbers were
derived for maximum flexibility and work for a system clock frequency
between 54 MHz and 133 MHz.
To re-write the EBIU_SDGCTL register within the user code, first, place the
chip in self-refresh (see the ADSP-BF538/ADSP-BF538F Blackfin Processor
Hardware Reference). Clearing the appropriate checkbox on the Target
Options dialog box, which is accessible through the Settings pull-down
menu, disables the automatic and allows manual configuration. For more
information, see online Help.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings1
1 54 MHz <=SCLK <= 133 MHz.
Register Value Function
EBIU_SDGCTL 0x009199 8D Calculated with SCLK = 133MHz
16-bit data path
External buffering timing disabled
tWR = 2 SCLK cycles
tRCD = 3 SCLK cycles
tRP = 3 SCLK cycles
tRAS = 6 SCLK cycles
pre-fetch disabled
CAS latency = 3 SCLK cycles
SCLK1 disabled
EBIU_SDBCTL 0x000000 25 Bank 0 enabled
Bank 0 size = 64MB
Bank 0 column address width = 10 bits
EBIU_SDRRC 0x000003A0 Calculated with SCLK = 54MHz
RDIV = 416 clock cycles