Analog Devices ADSP-BF538F

ADSP-BF538F EZ-KIT Lite Evaluation System Manual xi

Preface

The board features:

• Analog Devices ADSP-BF538F processor

DCore performance up to 600 MHz

DExternal bus performance to 133 MHz

D182-pin mini-BGA package

D25 MHz crystal

• Synchronous dynamic random access memory (SDRAM)

DMT48LC32M8 – 64 MB (8M x 8-bits x 4 banks) x 2 chips

• Flash memory

D4MB (2M x 16-bits)

• Analog audio interface

DAD1871 96 kHz analog-to-digital codec (ADC)

DAD1854 96 kHz digital-to-audio codec (DAC)

D1 input stereo jack

D1 output stereo jack

• Controller Area Network (CAN) interface

DPhilips TJA1041 high-speed CAN transceiver

• National Instruments Educational Laboratory Virtual Instrumen-

tation Suite (ELVIS) interface

DLabVIEW™-based virtual instruments

DMultifunction data acquisition device

DBench-top workstation and prototype board

Contents

Main Page Regulatory Compliance Page CONTENTS PREFACE USING ADSP-BF538F EZ-KIT LITE ADSP-BF538F EZ-KIT LITE HARDWARE REFERENCE Page ADSP-BF538F EZ-KIT LITE BILL OF MATERIALS ADSP-BF538F EZ-KIT LITE SCHEMATIC INDEX PREFACE L Page Page Purpose of This Manual Intended Audience Manual Contents Whats New in This Manual Technical or Customer Support Supported Processors Product Information MyAnalog.com Processor Product Information Related Documents L Online Technical Documentation Page Printed Manuals ADSP-BF538F EZ-KIT Lite Evaluation System Manual xxi Preface Notation Conventions L a [ Page 1 USING ADSP-BF538F EZ-KIT LITE Page Package Contents Default Configuration Page Installation and Session Startup L Evaluation License Restrictions L Memory Map SDRAM Interface 1-8 ADSP-BF538F EZ-KIT Lite Evaluation System Manual SDRAM Interface Table 1-1. EZ-KIT Lite Evaluation Board Memory Map Page Flash Memory CAN Interface ELVIS Interface Audio Interface LEDs and Push Buttons Example Programs Background Telemetry Channel 2 ADSP-BF538F EZ-KIT LITE HARDWARE REFERENCE System Architecture 2-2 ADSP-BF538F EZ-KIT Lite Evaluation System Manual System Architecture Timers CAN TWI JTAG Agent External Bus Interface Unit SPORT0 Interface SPI Interface UART Interface Programmable Flags ADSP-BF538F EZ-KIT Lite Evaluation System Manual 2-5 ADSP-BF538F EZ-KIT Lite Hardware Reference System Architecture 2-6 ADSP-BF538F EZ-KIT Lite Evaluation System Manual ADSP-BF538F EZ-KIT Lite Evaluation System Manual 2-7 ADSP-BF538F EZ-KIT Lite Hardware Reference UART Port Expansion Interface [ JTAG Emulation Port Jumper and Switch Settings CAN Enable Switch (SW2) UART Enable Switch (SW4) Push Button Enable Switch (SW5) Flash Enable Switch (SW6) FCE Enable Switch (SW14) Audio Enable Switch (SW7) Boot Mode Select Switch (SW3) PPI Direction Control (JP1) UART Loop Jumper (JP9) ELVIS Oscilloscope Configuration Switch (SW1) ELVIS Function Generator Configuration Switch (SW8) ELVIS Voltage Selection Jumper (JP6) [ ELVIS Select Jumper (JP8) LEDs and Push Buttons Reset Push Button (SW9) Programmable Flag Push Buttons (SW1013) Power LED (LED7) Reset LED (LED8) User LEDs (LED26) USB Monitor LED (ZLED3) L Page Page Power Connector (J7) Expansion Interface Connectors (J13) JTAG Connector (ZP4) L SPORT0 and SPORT1 Connectors (P6 and P7) PPI Connector (P8) SPI Connector (P9) 2-Wire Interface Connector (P10) TIMERS Connector (P11) UART1 Connector (P12) Page ADSP-BF538F EZ-KIT Lite Evaluation System Manual A-1 A ADSP-BF538F EZ-KIT LITE BILL OF MATERIALS The bill of materials corresponds to ADSP-BF538F EZ-KIT Lite Sche- matic on page B-1. A-2 ADSP-BF538F EZ-KIT Lite Evaluation System Manual ADSP-BF538F EZ-KIT Lite Evaluation System Manual A-3 A-4 ADSP-BF538F EZ-KIT Lite Evaluation System Manual ADSP-BF538F EZ-KIT Lite Evaluation System Manual A-5 A-6 ADSP-BF538F EZ-KIT Lite Evaluation System Manual ADSP-BF538F EZ-KIT Lite Evaluation System Manual A-7 A-8 ADSP-BF538F EZ-KIT Lite Evaluation System Manual SCHEMATIC ADSP-BF538F EZ-KIT LITE TITLE RTC DSP 13210-15-2007_13:17 DSP POWER 13310-15-2007_13:17 (8M x 8 x 4 banks) x 2 chips 0x0000 0000 0x03FF FFFF SDRAM AND FLASH 10-15-2007_13:17 4 13 Memory Map ADC AND AUDIO IN LABEL "LINE IN" ADC 10-15-2007_13:17 5 13 ADC RIGHT SW7: Audio Selection Switch DAC LABEL "LINE OUT" DAC AND AUDIO OUT LABEL "CAN" CAN SW2: CAN Enable Switch CAN 10-15-2007_13:17 7 13 LABEL "PB1" PUSH BUTTONS, LEDS AND BOOT MODE 4-29-2008_15:55 8 13 LABEL "PB2" LABEL "PB4" LABEL "PB3" DSP CORE VOLTAGE & CURRENT ELVIS Voltage Selection Jumper ELVIS INTERFACE 13910-15-2007_13:17 NI ELVIS ID 33 (0010 0001) DSP JTAG HEADER Engineer to Engineer Note EE-68 which can be found at EXPANSION INTERFACE & JTAG http://www.analog.com All USB interface circuitry is considered proprietary and has been omitted from this schematic. (UART 0) SERIAL PORT STAMP CONNECTORS 10-15-2007_13:17 11 13 SPI MISC CONNECTORS SPI 1 SPI 2 131210-15-2007_13:17 UART 1 UART 2 TWI1 5V@5A POWER 131310-15-2007_13:17 3.3V@3A LABEL "VDDINT" LABEL "GND" INDEX Numerics A B C I-2 ADSP-BF538F EZ-KIT Lite Evaluation System Manual D E F G ADSP-BF538F EZ-KIT Lite Evaluation System Manual I-3 H I J L I-4 ADSP-BF538F EZ-KIT Lite Evaluation System Manual R S ADSP-BF538F EZ-KIT Lite Evaluation System Manual I-5 T U V Page Search: Processors View all Products Technical Support News and Events Page Embedded Processing & DSP Home Blackfin SHARC TigerSHARC ADSP-21xx Learning and Development Purchasing Information Software and Reference Designs News & Events Technical Support Page Log In: myAnalog Search: Processors View all Products Technical Support News and Events Page Technical Library Page View Cart | My Account | Log In Search: Contact Us | Print this Page | Email this Page Blackfin Processor Development Tools Processor Evaluation Platform Emulator Software Third Party Tools