2.6.3 Panel Interface Drive Strength
As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details.
Table 14. Panel Interface Pad Drive Strength | |
|
|
Value (4 bits) | Drive Strength in mA |
0 | Outputs are in |
1 | 2mA |
2 | 4mA |
3 | 6mA |
4 | 8mA |
5 | 10mA |
6 | 12mA |
7 | 14mA |
8 | 16mA |
9 | 18mA |
10,11,12,13,14,15 | 20mA |
2.7 Host Interface
The host microcontroller interface of the gmZAN1 has two modes of operation: gmB120 compatible mode, and a 4- bit serial interface mode.
zGmB120 compatible
z
When the chip is configured for
In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must be low for at least 100ns after the CVDD has become stable (between +3.15V and +3.45V) in order to reset the chip to a known state.
The gmZAN1 chip has an
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