2.6.2.1 State 0 (Power Off)
The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled.
2.6.2.2 State 1 (Power On)
Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is forced low (inactive).
2.6.2.3 State 2 (Panel Drive Enabled)
Intermediate step 2. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is active.
2.6.2.4 State 3 (Panel Fully Active)
This is the final step in the power up sequence, with Ppower and Pbias high (active), and the panel interface active. PM is kept in this state until the internal TFT_Enable signal controlled by Panel Control register is disabled. The panel can be disabled through either an API call under program control or automatically by the gmZAN1 to prevent damage to the panel.
Figure 9. Panel Power Sequence
TFT_EN Bit | t1 |
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(register bit) |
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PPWR Output |
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| t4 |
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| t6 |
Data/Controls Signals | t2 |
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| t5 |
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PBias Output |
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| t3 |
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| <State0> | <State1> | <State2> | <State3> | <State2> | <State1> <State0> |
In Figure 9 above, t2=t6 and t3=t5. t1,t2,t3 and t4 are independently programmable from one to eight steps in length. The length of each step is in the range of 511 * X* (TCLKi cycle) or (TCLKi cycle) * 32193 *X, where X is any positive integer value equal to or less than 256. TCLKi is the reference clock to the gmZAN1 chip, and ranges from 14.318 MHz to 50 MHz in frequency. This programmability provides enough flexibility to meet a wide range of power sequencing requirements by various panels.
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