Clock Recovery Circuit | AOC P/N : 41A50-144 guide

The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range.

The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency divided by N is locked to SCLK frequency divided by M. The value M and N are calculated and programmed in the register by firmware. The value M should be close to the Source Htotal value.

Figure 4. Clock Recovery Circuit

Sample

Hsync Phase

Delay

DDS Digital
Clock
Synthesis
	DDS Output
Course	Analog
Adjust	PLL & VCO
Fine
Adjust
	PLL
	Divider
	÷ m
	Source
	Horizontal
	Total Divider

VCO

Output

Prescaler ÷ 2 (or 1)

Clock

Divider SCLK

÷ n

TCLK

Analog

PLL & VCO

Post Scale

÷ 2 (or 1)

RCLK

PLL Divider ÷ n (2 to 8)

PLL Divider

÷ 2 (or 1)

P/N : 41A50-144 specifications

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AOC P/N : 41A50-144 service manual Clock Recovery Circuit

Models: P/N : 41A50-144

Figure 4. Clock Recovery Circuit

P/N : 41A50-144 specifications