AOC P/N : 41A50-144 Functional Description, Overall Architecture, Clock Recovery Circuit

2. FUNCTIONAL DESCRIPTION

Figure 3 below shows the main functional blocks inside the gmZAN1

2.1 Overall Architecture

Figure 3. Block Diagram for gmZAN1

				On-Screen
				Display
				Control
Analog	Triple	Source	Scaling	Gamma	Panel
RGB	ADC	Timing	Engine	Control	Timing	Panel
		Measurement		(CLUT)	Control
		/ Generation		+
				Dither
MCU		Host		Clock	Pixel
		Interface		Recovery	Clock
					Generator
					Clock
					Reference

2.2 Clock Recovery Circuit

The gmZAN1 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer and an analog PLL. The clock recovery circuit generates the clock used to sample analog RGB data (SCLK or source clock). This circuit is locked to the HSUNC of the incoming video signal. The RCLK generated from the TCLK input is used as a reference clock.

The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK period multiplied by the Source Horizontal Total value (as programmed into the registers) locks to the rising edge of the Hsync input. Even though the initial SCLK frequency and the final SCLK frequency are as far apart as 60MHz , locking can be achieved in less than 1ms across the operation voltage/temperature range.

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