Texas Instruments Carrier 23xrv Manual for TMS320C6722, TMS320C6726, and TMS320C6727 Systems

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.14.3 SPI Electrical Data/Timing

4.14.3.1 Serial Peripheral Interface (SPI) Timing

Table 4-25through Table 4-32assume testing over recommended operating conditions (see Figure 4-33through Figure 4-36).

Table 4-25. General Timing Requirements for SPIx Master Modes(1)

NO.

1tc(SPC)M

2 tw(SPCH)M

3 tw(SPCL)M

Cycle Time, SPIx_CLK, All Master Modes

Pulse Width High, SPIx_CLK, All Master Modes

Pulse Width Low, SPIx_CLK, All Master Modes

MIN

greater of 8P or 100 ns

greater of 4P or 45 ns

greater of 4P or 45 ns

MAX UNIT

256P ns

ns

ns

4td(SIMO_SPC)M

5td(SPC_SIMO)M

6toh(SPC_SIMO)M

7tsu(SOMI_SPC)M

8tih(SPC_SOMI)M

Delay, initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK(2)

Delay, subsequent bits valid on SPIx_SIMO after transmit edge of SPIx_CLK

Output hold time, SPIx_SIMO valid after receive edge of SPIxCLK, except for final bit(3)

Input Setup Time,

SPIx_SOMI valid before receive edge of SPIx_CLK

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK rising

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK falling

Polarity = 1, Phase = 1, from SPIx_CLK rising

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK rising

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK falling

Polarity = 0, Phase = 0, to SPIx_CLK falling

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK rising

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK rising

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK falling

4P

0.5tc(SPC)M + 4P

4P

0.5tc(SPC)M + 4P

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 5

0.5P + 5

0.5P + 5

0.5P + 5

ns

15

15

ns

15

15

ns

ns

ns

(1)P = SYSCLK2 period

(2)First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.

(3)The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.

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