TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.12.3 UHPI Electrical Data/Timing

4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing

Table 4-15and Table 4-16assume testing over recommended operating conditions (see Figure 4-21through Figure 4-24).

Table 4-15. UHPI Read and Write Timing Requirements(1) (2)

NO.

 

 

MIN

MAX UNIT

9

tsu(HASL-DSL)

Setup time, UHPI_HAS low before DS falling edge

5

ns

10

th(DSL-HASL)

Hold time, UHPI_HAS low after DS falling edge

2

ns

11

tsu(HAD-HASL)

Setup time, HAD valid before UHPI_HAS falling edge

5

ns

12

th(HASL-HAD)

Hold time, HAD valid after UHPI_HAS falling edge

5

ns

13

tw(DSL)

Pulse duration, DS low

15

ns

14

tw(DSH)

Pulse duration, DS high

2P

ns

15

tsu(HAD-DSL)

Setup time, HAD valid before DS falling edge

5

ns

16

th(DSL-HAD)

Hold time, HAD valid after DS falling edge

5

ns

17

tsu(HD-DSH)

Setup time, HD valid before DS rising edge

5

ns

18

th(DSH-HD)

Hold time, HD valid after DS rising edge

0

ns

37

tsu(HCSL-DSL)

Setup time, UHPI_HCS low before DS falling edge

0

ns

38

th(HRDYH-DSL)

Hold time, DS low after UHPI_HRDY rising edge

1

ns

(1)P = SYSCLK2 period

(2)DS refers to HSTROBE. HD refers to UHPI_HD[31:0]. HDS refers to UHPI_HDS[1] or UHPI_HDS[2]. HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.

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Peripheral and Electrical Specifications

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Texas Instruments TMS320C6726 Uhpi Electrical Data/Timing, Universal Host-Port Interface Uhpi Read and Write Timing