Texas Instruments TMS320C6727, TMS320C6722 Additional1 SPI Slave Timings, 4-Pin Enable Option2

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-30. Additional(1) SPI Slave Timings, 4-Pin Enable Option(2) (3)

NO.

Delay from final

24 td(SPC_ENAH)S SPIx_CLK edge to slave deasserting SPIx_ENA.

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

MIN		MAX UNIT
P – 10	3P	+ 15
0.5tc(SPC)M + P – 10	0.5tc(SPC)M + 3P	+ 15
		ns
P – 10	3P	+ 15
0.5tc(SPC)M + P – 10	0.5tc(SPC)M + 3P	+ 15

(1)These parameters are in addition to the general timings for SPI slave modes (Table 4-26).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 4-31. Additional(1) SPI Slave Timings, 4-Pin Chip Select Option(2) (3)

NO.

25td(SCSL_SPC)S

Required delay from SPIx_SCS asserted at slave to first SPIx_CLK edge at slave.

MIN	MAX UNIT
P	ns

26td(SPC_SCSH)S

Required delay from final SPIx_CLK edge before SPIx_SCS is deasserted.

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

0.5tc(SPC)M + P + 10

P + 10

ns

0.5tc(SPC)M + P + 10

P + 10

27tena(SCSL_SOMI)S

28tdis(SCSH_SOMI)S

Delay from master asserting SPIx_SCS to slave driving SPIx_SOMI valid

Delay from master deasserting SPIx_SCS to slave 3-stating SPIx_SOMI

P + 15	ns
P + 15	ns

(1)These parameters are in addition to the general timings for SPI slave modes (Table 4-26).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

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