Io/I Ipd | Texas Instruments TMS320C6722, TMS320C6727, TMS320C6726

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 2-12. Terminal Functions (continued)

	SIGNAL NAME	RFP	GDH/	TYPE (1)	PULL (2)	GPIO (3)	DESCRIPTION
	SIGNAL NAME	RFP	ZDH	TYPE (1)	PULL (2)	GPIO (3)	DESCRIPTION
			ZDH
	External Memory Interface (EMIF) Data Bus / Universal Host-Port Interface (UHPI) Address Bus Option
	EM_D[0]	52	T8	IO	-	N
	EM_D[1]	51	R8	IO	-	N
	EM_D[2]	49	R7	IO	-	N
	EM_D[3]	48	T6	IO	-	N
	EM_D[4]	46	R6	IO	-	N
	EM_D[5]	45	T5	IO	-	N
	EM_D[6]	43	R5	IO	-	N
	EM_D[7]	41	T4	IO	-	N	EMIF Data Bus [Lower 16 Bits]
	EM_D[8]	66	R13	IO	-	N	EMIF Data Bus [Lower 16 Bits]
	EM_D[8]	66	R13	IO	-	N
	EM_D[9]	64	T12	IO	-	N
	EM_D[10]	63	R12	IO	-	N
	EM_D[11]	61	T11	IO	-	N
	EM_D[12]	59	R11	IO	-	N
	EM_D[13]	58	R10	IO	-	N
	EM_D[14]	56	T9	IO	-	N
	EM_D[15]	55	R9	IO	-	N
	EM_D[16]/UHPI_HA[0]	-	N7	IO/I	IPD	N
	EM_D[17]/UHPI_HA[1]	-	P6	IO/I	IPD	N
	EM_D[18]/UHPI_HA[2]	-	N6	IO/I	IPD	N
	EM_D[19]/UHPI_HA[3]	-	P5	IO/I	IPD	N
	EM_D[20]/UHPI_HA[4]	-	P4	IO/I	IPD	N
	EM_D[21]/UHPI_HA[5]	-	P3	IO/I	IPD	N
	EM_D[22]/UHPI_HA[6]	-	N4	IO/I	IPD	N
	EM_D[23]/UHPI_HA[7]	-	R2	IO/I	IPD	N	EMIF Data Bus [Upper 16 Bits (IO)] or
	EM_D[24]/UHPI_HA[8]	-	P11	IO/I	IPD	N	UHPI Address Input (I)
	EM_D[25]/UHPI_HA[9]	-	N11	IO/I	IPD	N
	EM_D[26]/UHPI_HA[10]	-	P10	IO/I	IPD	N
	EM_D[27]/UHPI_HA[11]	-	N10	IO/I	IPD	N
	EM_D[28]/UHPI_HA[12]	-	P9	IO/I	IPD	N
	EM_D[29]/UHPI_HA[13]	-	N9	IO/I	IPD	N
	EM_D[30]/UHPI_HA[14]	-	N8	IO/I	IPD	N
	EM_D[31]/UHPI_HA[15]	-	P7	IO/I	IPD	N

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Texas Instruments TMS320C6722, TMS320C6727, TMS320C6726 warranty Io/I Ipd

Contents

Features TMS320C6727, TMS320C6726, TMS320C6722 DSPs Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance Characteristics Hardware Features Device CharacteristicsCharacteristics of the C672x Processors C6726 Enhanced C67x+ CPU CPU Data Paths CPU Interrupt Assignments CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU Instruction FLOATING-POINT Improves Operation Internal Program/Data ROM and RAM Byte Bank Program Cache Control Registers Cache ModeProgram Cache Register Name Byte Address Description High-Performance Crossbar Switch Block Diagram of Crossbar Switch Bus Bridges Label Bridge Description Master Clock Target Clock BIT no Name Reset Value Read Write Description Csprst C672x Memory Map Memory Map SummaryFfff Boot Mode Uhpihcs Boot ModesRequired Boot Pin Settings at Device Reset SPI0SIMO SPI0CLK BIT no Name Description PINCAP7 PINCAP15 Pin Assignments Pin Maps Pin Low-Profile Quad Flatpack RFP Suffix-Top View 12. Terminal Functions Signal Name RFP GDHTerminal Functions ZDH IO/I IPD Description ZDH AFSR0 AHCLKR0/AHCLKR1ACLKR0 AHCLKX0/AHCLKX2 Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP Package Development Support DevelopmentDevice Support Device Family TMS 320 C6727 GDH a 250Prefix Device Speed Range Package Type ‡ § Documentation Support C672x devices are documented in the tools v6.0 documentation Options for Configuring SPI0, I2C0, and I2C1 Device Configuration RegistersDevice-Level Configuration Registers Peripheral Pin Multiplexing Options Configuration Option Peripheral Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Peripheral Pin Multiplexing Control Priority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third Priority Recommended Operating Conditions1 Electrical SpecificationsAbsolute Maximum Ratings1 Unit II, IOZ Parameter Test Conditions MIN TYP MAX UnitDvdd GDH, CV Parameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Timing Requirements ResetReset Electrical Data/Timing MIN MAX Unit Dual Data Movement Accelerator dMAX DMAX Device-Specific Information REQ DMAXRAM REQ RAM Submit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event Description DMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific Information Emras ResetDSP Emif Emwe EMWEDQM0 EmcasEmclk EMWEDQM1 Emif Peripheral Registers Descriptions Emif Registers Emif Sdram Interface Timing Requirements Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Parameter MIN MAX Unit Emif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1 Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 13. Emwait Timing Requirements Uhpi Device-Specific Information 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Major Modes on C672x Uhpihasb DSPUHPIHD16/HHWIL Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C Uhpi Peripheral Registers Descriptions 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Internal Registers BIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENA Hpiamsb Description BIT no Name Reset Read Value Write318 Reserved Hpiaumb Description Universal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO 17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins Comments Register Byte Description Name Address Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions McASP Internal Registers DITCSRA0 XclkchkXevtctl DITCSRA1 0x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 AMUTEIN1 Description AMUTEIN2 AMUTEIN2 Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B Serial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific Information Master SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P 29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information 15.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address Inter-Integrated Circuit I2C Timing 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing 34. I2C Input Timing Requirements Parameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt 36. RTI Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions RTI Internal Registers Rtidwdprld RtiintflagRtidwdctrl Rtiwdstatus External Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator Components Clock Electrical Data/Timing 39. Clkin Timing Requirements Phase-Locked Loop PLL PLL Device-Specific Information Board Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions EMI PLL Registers Descriptions 41. PLL Controller Registers Spio CODEC, DIRADC, DAC, DSD RTI ADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff Height PowerPAD PCB Footprint Packaging InformationPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice