Parameter Information | Texas Instruments TMS320C6726, TMS320C6727

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.5 Parameter Information

4.5.1Parameter Information Device-Specific Information

42Ω

4.0pF

3.5nH

1.85pF

Tester Pin Electronics

Transmission Line

Z0 = 50 Ω

(see note)

Data Sheet Timing Reference Point

Output

Under

Test

Device Pin (see note)

A.The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not neccessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 4-1. Test Load Circuit for AC Timing Measurements

4.5.1.1 Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.

Vref = 1.5 V

Figure 4-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks.

Vref = VIH MIN (or VOH MIN)

Vref = VIL MAX (or VOL MAX)

Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels

4.5.1.2 Signal Transition Rates

All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).

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Peripheral and Electrical Specifications

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Texas Instruments TMS320C6726, TMS320C6727 Parameter Information Device-Specific Information, Tester Pin Electronics

Contents

TMS320C6727, TMS320C6726, TMS320C6722 DSPs Features Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics Contents C6726 Device CharacteristicsCharacteristics of the C672x Processors Hardware Features CPU Data Paths Enhanced C67x+ CPU Instruction FLOATING-POINT Improves Operation CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU CPU Interrupt Assignments Byte Bank Internal Program/Data ROM and RAM Register Name Byte Address Description Cache ModeProgram Cache Program Cache Control Registers Block Diagram of Crossbar Switch High-Performance Crossbar Switch Label Bridge Description Master Clock Target Clock Bus Bridges Csprst BIT no Name Reset Value Read Write Description Ffff Memory Map SummaryC672x Memory Map SPI0SIMO SPI0CLK Boot ModesRequired Boot Pin Settings at Device Reset Boot Mode Uhpihcs PINCAP7 BIT no Name Description PINCAP15 Pin Maps Pin Assignments Pin Low-Profile Quad Flatpack RFP Suffix-Top View ZDH Signal Name RFP GDHTerminal Functions 12. Terminal Functions IO/I IPD Description ZDH AHCLKX0/AHCLKX2 AHCLKR0/AHCLKR1ACLKR0 AFSR0 Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH Package Device Support DevelopmentDevelopment Support Package Type ‡ § TMS 320 C6727 GDH a 250Prefix Device Speed Range Device Family Documentation Support C672x devices are documented in the tools v6.0 documentation Peripheral Pin Multiplexing Options Device Configuration RegistersDevice-Level Configuration Registers Options for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing Control Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Configuration Option Peripheral PIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed Pins Unit Electrical SpecificationsAbsolute Maximum Ratings1 Recommended Operating Conditions1 GDH, CV Parameter Test Conditions MIN TYP MAX UnitDvdd II, IOZ Tester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing MIN MAX Unit ResetReset Electrical Data/Timing Reset Timing Requirements DMAX Device-Specific Information Dual Data Movement Accelerator dMAX REQ RAM DMAXRAM REQ Submit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input Assignments Byte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts Emif Device-Specific Information External Memory Interface Emif Emwe ResetDSP Emif Emras EMWEDQM1 EmcasEmclk EMWEDQM0 Emif Registers Emif Peripheral Registers Descriptions Parameter MIN MAX Unit Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Emif Sdram Interface Timing Requirements Emif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1 Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 13. Emwait Timing Requirements Uhpi Major Modes on C672x 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Device-Specific Information Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT DSPUHPIHD16/HHWIL Uhpihasb External Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode Uhpi Internal Registers 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Peripheral Registers Descriptions Bytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value Write Hpiaumb Description BIT no Name Reset Read Value Write318 Reserved Hpiamsb Description 15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSP McASP Internal Registers Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions Register Byte Description Name Address DITCSRA1 XclkchkXevtctl DITCSRA0 0x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 Description AMUTEIN1 AMUTEIN2 AMUTEIN2 22. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output Timings SPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1 Slave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 29. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C1 Register Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions 34. I2C Input Timing Requirements 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing Inter-Integrated Circuit I2C Timing I2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information RTI Internal Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions 36. RTI Registers Rtiwdstatus RtiintflagRtidwdctrl Rtidwdprld 38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin 39. Clkin Timing Requirements Clock Electrical Data/Timing PLL Device-Specific Information Phase-Locked Loop PLL EMI Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions Board 41. PLL Controller Registers PLL Registers Descriptions RTI CODEC, DIRADC, DAC, DSD Spio ADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff Height Packaging Information PowerPAD PCB FootprintPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice