Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, Case 1. HPIC or HPIA read

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-16. UHPI Read and Write Switching Characteristics(1) (2)

NO.

1td(DSL-HDV)

2tdis(DSH-HDV)

3ten(DSL-HDD)

4td(DSL-HRDYH)

5td(DSH-HRDYH)

6td(DSL-HRDYL)

PARAMETER		MIN	MAX	UNIT
	Case 1. HPIC or HPIA read	1	15
	Case 2. HPID read with no		9 * 2H + 20(3)
	auto-increment
Delay time, DS low to HD valid	Case 3. HPID read with		9 * 2H + 20(3)	ns
	auto-increment and read FIFO
	initially empty
	Case 4. HPID read with
	auto-increment and data previously	1	15
	prefetched into the read FIFO
Disable time, HD high-impedance from DS high		1	4	ns
Enable time, HD driven from DS low		3	15	ns
Delay time, DS low to UHPI_HRDY high			12	ns
Delay time, DS high to UHPI_HRDY high			12	ns
	Case 1. HPID read with no		10 * 2H + 20(3)
	auto-increment
Delay time, DS low to UHPI_HRDY
	Case 2. HPID read with			ns
low			10 * 2H + 20(3)
	auto-increment and read FIFO

initialy empty

7td(HDV-HRDYL)

34td(DSH-HRDYL)

35td(DSL-HRDYL)

36td(HASL-HRDYH)

Delay time, HD valid to UHPI_HRDY low		0			ns
	Case 1. HPIA write	5	* 2H	+ 20(3)
Delay time, DS high to	Case 2. HPID read with				ns
UHPI_HRDY low	auto-increment and read FIFO	5	* 2H	+ 20(3)
	initially empty
Delay time, DS low to UHPI_HRDY low for HPIA write and FIFO not		40	* 2H	+ 20(3)	ns
empty
Delay time, UHPI_HAS low to UHPI_HRDY high				12	ns

(1)H = 0.5 * SYSCLK2 period

(2)DS refers to HSTROBE. HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.

(3)Max delay is a best case, assuming no delays due to resource conflicts between UHPI and dMAX or CPU. UHPI_HRDY should always be used to indicate when an access is complete instead of relying on these parameters.

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