Texas Instruments TMS320C6727, TMS320C6726, TMS320C6722, 1.Reset Timing Requirements

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.8 Reset

A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions.

4.8.1Reset Electrical Data/Timing

Table 4-1assumes testing over recommended operating conditions.

Table 4-1. Reset Timing Requirements

NO.

1 tw(RSTL)

2tsu(BPV-RSTH)

3th(RSTH-BPV)

	MIN	MAX UNIT
Pulse width, RESET low	100	ns
Setup time, boot pins valid before RESET high	20	ns
Hold time, boot pins valid after RESET high	20	ns

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