McASP Configurations on C672x DSP | Texas Instruments TMS320C6727

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

The three McASPs on C672x have different configurations (see Table 4-17). NOTE: McASP2 is not available on the C6722.

Table 4-17. McASP Configurations on C672x DSP

McASP	DIT	CLOCK PINS	DATA PINS	COMMENTS
McASP0	No	AHCLKX0/AHCLKX2, ACLKX0, AFSX0	Up to 16	AHCLKX0/AHCLKX2 share pin.
		AHCLKR0/AHCLKR1, ACLKR0, AFSR0		AHCLKR0/AHCLKR1 share pin.
McASP1	No	AHCLKX1, ACLKX1, AFSX1, ACLKR1, AFSR1	Up to 6	AHCLKR0/AHCLKR1 share pin
McASP2	Yes	ACLKX2, AFSX2, AHCLKR2, ACLKR2, AFSR2	Up to 2	Full functionality on C6727. On C6726,
		(Only available on the C6727.)		functions only as DIT since only
				AHCLKX0/AHCLKX2 is available.
				Not available on the C6722.

NOTE: The McASPs do not have dedicated AMUTEINx pins. Instead they can select one of the pins listed in Table 4-19, Table 4-20, and Table 4-21to use as a mute input.

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Peripheral and Electrical Specifications

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Texas Instruments TMS320C6727, TMS320C6722 warranty McASP Configurations on C672x DSP, DIT Clock Pins Data Pins Comments

Contents

TMS320C6727, TMS320C6726, TMS320C6722 DSPs Features Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics Contents Characteristics of the C672x Processors Device CharacteristicsHardware Features C6726 CPU Data Paths Enhanced C67x+ CPU New Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsCPU Interrupt Assignments Instruction FLOATING-POINT Improves Operation Byte Bank Internal Program/Data ROM and RAM Program Cache Cache ModeProgram Cache Control Registers Register Name Byte Address Description Block Diagram of Crossbar Switch High-Performance Crossbar Switch Label Bridge Description Master Clock Target Clock Bus Bridges Csprst BIT no Name Reset Value Read Write Description Memory Map Summary C672x Memory MapFfff Required Boot Pin Settings at Device Reset Boot ModesBoot Mode Uhpihcs SPI0SIMO SPI0CLK PINCAP7 BIT no Name Description PINCAP15 Pin Maps Pin Assignments Pin Low-Profile Quad Flatpack RFP Suffix-Top View Terminal Functions Signal Name RFP GDH12. Terminal Functions ZDH IO/I IPD Description ZDH ACLKR0 AHCLKR0/AHCLKR1AFSR0 AHCLKX0/AHCLKX2 Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH Package Development Development SupportDevice Support Prefix Device Speed Range TMS 320 C6727 GDH a 250Device Family Package Type ‡ § Documentation Support C672x devices are documented in the tools v6.0 documentation Device-Level Configuration Registers Device Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing Options Options for Configuring Emif and Uhpi C6727 Only Options for Configuring SPI1, McASP0, and McASP1 Data PinsConfiguration Option Peripheral Peripheral Pin Multiplexing Control PIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed Pins Absolute Maximum Ratings1 Electrical SpecificationsRecommended Operating Conditions1 Unit Dvdd Parameter Test Conditions MIN TYP MAX UnitII, IOZ GDH, CV Parameter Information Parameter Information Device-Specific InformationTester Pin Electronics Timing Parameter Symbology Power Supplies Power-Supply SequencingPower-Supply Decoupling Reset Electrical Data/Timing ResetReset Timing Requirements MIN MAX Unit DMAX Device-Specific Information Dual Data Movement Accelerator dMAX RAM DMAXREQ REQ RAM Submit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input Assignments DMAX Configuration Registers DMAX Peripheral Registers DescriptionsByte Address Register Name Description External Interrupts Emif Device-Specific Information External Memory Interface Emif DSP Emif ResetEmras Emwe Emclk EmcasEMWEDQM0 EMWEDQM1 Emif Registers Emif Peripheral Registers Descriptions Emif Electrical Data/Timing Emif Sdram Interface Switching CharacteristicsEmif Sdram Interface Timing Requirements Parameter MIN MAX Unit Emif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1 Basic Sdram Write Operation Emclk Emras Emcas EmweBasic Sdram Read Operation 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 13. Emwait Timing Requirements Universal Host-Port Interface Uhpi C6727 Only 10. HPI Access Types Selected by UHPIHCNTL10Uhpi Device-Specific Information Uhpi Major Modes on C672x UHPIHD16/HHWIL DSPUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT External Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode Device-Level Configuration Registers Controlling Uhpi 11. Uhpi Configuration RegistersUhpi Peripheral Registers Descriptions Uhpi Internal Registers Bytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value Write 318 Reserved BIT no Name Reset Read Value WriteHpiamsb Description Hpiaumb Description Uhpi Electrical Data/Timing Universal Host-Port Interface Uhpi Read and Write Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 UHPIHDSx Read Write UHPIHA150Valid Read data Write data Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSP McASP Peripheral Registers Descriptions Device-Level Configuration Registers Controlling McASPRegister Byte Description Name Address McASP Internal Registers Xevtctl XclkchkDITCSRA0 DITCSRA1 0x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 313 ReservedAMUTEIN0 Description AMUTEIN1 Description AMUTEIN1 AMUTEIN2 AMUTEIN2 McASP Electrical Data/Timing Multichannel Audio Serial Port McASP Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output Timings SPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1 SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO Master SPISlave SPI 24. SPIx Configuration Registers SPI Peripheral Registers DescriptionsSPI0 SPI1 Register Name Description Byte Address SPI Electrical Data/Timing Serial Peripheral Interface SPI Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 29. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C1 33. I2Cx Configuration Registers 15.2 I2C Peripheral Registers DescriptionsRegister Name Description Byte Address 15.3 I2C Electrical Data/Timing 35. I2C Switching Characteristics1Inter-Integrated Circuit I2C Timing 34. I2C Input Timing Requirements 35. I2C Switching Characteristics ParameterI2CxSDA I2CxSCL Stop Start Repeated Real-Time Interrupt RTI Timer With Digital Watchdog 16.1 RTI/Digital Watchdog Device-Specific InformationWatchdog Key Register Bit Key RTI Interrupt 16.2 RTI/Digital Watchdog Registers Descriptions Device-Level Configuration Registers Controlling RTI36. RTI Registers RTI Internal Registers Rtidwdctrl RtiintflagRtidwdprld Rtiwdstatus 38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin 39. Clkin Timing Requirements Clock Electrical Data/Timing PLL Device-Specific Information Phase-Locked Loop PLL 40. Allowed PLL Operating Conditions Parameter Default Value Allowed Setting or RangeBoard EMI 41. PLL Controller Registers PLL Registers Descriptions ADC, DAC, DSD CODEC, DIRSpio RTI ADDS/CHANGES/DELETES Package Thermal Resistance Characteristics Thermal Characteristics for GDH/ZDH PackageThermal Characteristics for RFP Package Standoff Height Standoff Height Packaging Information PowerPAD PCB FootprintPage Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Page Important Notice