Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, 7.CFGPIN1 Register Bit Layout

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Figure 2-7shows the bit layout of the CFGPIN1 register and Table 2-11contains a description of the bits.

31							8
			Reserved
7	6	5	4	3	2	1	0
PINCAP15	PINCAP14	PINCAP13	PINCAP12	PINCAP11	PINCAP10	PINCAP9	PINCAP8

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004)

Table 2-11. CFGPIN1 Register Bit Field Description (0x4000 0004)

BIT NO.	NAME	DESCRIPTION
31:8	Reserved	Reads are indeterminate. Only 0s should be written to these bits.
7	PINCAP15	AXR0[5]/SPI1_SCS pin state captured on rising edge of RESET pin.
6	PINCAP14	AXR0[6]/SPI1_ENA pin state captured on rising edge of RESET pin.
5	PINCAP13	UHPI_HCS pin state captured on rising edge of RESET pin.
4	PINCAP12	UHPI_HD[0] pin state captured on rising edge of RESET pin.
3	PINCAP11	EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin.
2	PINCAP10	AFSX0 pin state captured on rising edge of RESET pin.
1	PINCAP9	AFSR0 pin state captured on rising edge of RESET pin.
0	PINCAP8	AXR0[0] pin state captured on rising edge of RESET pin.

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