Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, 25.McASP Block Diagram

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.13Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

∙Flexible clock and frame sync generation logic and on-chip dividers

∙Up to sixteen transmit or receive data pins and serializers

∙Large number of serial data format options, including:

–TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).

–Time slots of 8,12,16, 20, 24, 28, and 32 bits.

–First bit delay 0, 1, or 2 clocks.

–MSB or LSB first bit order.

–Left- or right-aligned data words within time slots

∙DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.

∙Extensive error-checking and mute generation logic

∙All unused pins GPIO-capable

Peripheral

Configuration

Bus

McASP

DMA Bus (Dedicated)

		Pins
GIO	Receive Logic	AHCLKRx
	Clock/Frame Generator	ACLKRx
Control
	State Machine	AFSRx
	Clock Check and	AMUTEINx
DIT RAM	Error Detection	AMUTEx
384 C
384 U	Transmit Logic	AFSXx
Optional
	Clock/Frame Generator	ACLKXx
	State Machine	AHCLKXx
Transmit	Serializer 0	AXRx[0]
Formatter
	Serializer 1	AXRx[1]
Receive	Serializer y	AXRx[y]
Formatter
	McASPx (x = 0, 1, 2)

Function

Receive Master Clock Receive Bit Clock

Receive Left/Right Clock or Frame Sync

The McASPs DO NOT have dedicated AMUTEINx pins.

Transmit Left/Right Clock or Frame Sync Transmit Bit Clock

Transmit Master Clock

Transmit/Receive Serial Data Pin

Transmit/Receive Serial Data Pin

Transmit/Receive Serial Data Pin

Figure 4-25. McASP Block Diagram

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