Texas Instruments TMS320C6727, TMS320C6726, TMS320C6722, 5.CFGBRIDGE Register Bit Layout, Name

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Figure 2-5shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7contains a description of the bits.

31					16
			Reserved
15				1	0
			Reserved		CSPRST
					R/W, 1
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024)
		Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024)
BIT NO.	NAME	RESET VALUE	READ WRITE	DESCRIPTION
31:1	Reserved	N/A	N/A	Reads are indeterminate. Only 0s should be written to these bits.
0	CSPRST	1	R/W	Resets the CSP Bridge (BR2 in Figure 2-4).
				1 = Bridge Reset Asserted
				0 = Bridge Reset Released

CAUTION

The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1 and SYSCLK2 and must be released before any accesses to the CSP bridge occur from either the dMAX or the UHPI.

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