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TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

The dMAX controller comprises:

∙Event and interrupt processing registers

∙Event encoder

∙High-priority event Parameter RAM (PaRAM)

∙Low-priority event Parameter RAM (PaRAM)

∙Address-generation hardware for High-Priority Events – MAX0 (HiMAX)

∙Address-generation hardware for Low-Priority Events – MAX1 (LoMAX)

The TMS320C672x Peripheral Bus Structure can be described logically as a Crossbar Switch with five master ports and five slave ports. When accessing the slave ports, the MAX0 (HiMAX) module is always given the highest priority followed by the MAX1 (LoMAX) module. In other words, in case several masters (including MAX0 and MAX1) attempt to access same slave port concurrently, the MAX0 will be given the highest priority followed by MAX1.

Event signals are connected to bits of the dMAX Event Register (DER), and the bits in the DER reflect the current state of the event signals. An event is defined as a transition of the event signal. The dMAX Event Flag Register (DEFR) can be programmed, individually for each event signal, to capture either low-to-high or high-to-low transitions of the bits in the DER (event polarity is individually programmable).

An event is a synchronization signal that can be used: 1) to either trigger dMAX to start a transfer, or 2) to

generate an interrupt to the CPU. All the events are sorted into two groups: low-priority event group and high-priority event group.

The High-Priority Data Movement Accelerator MAX0 (HiMAX) module is dedicated to serving requests coming from the high-priority event group. The Low-Priority Data Movement Accelerator MAX1 (LoMAX) module is dedicated to serving requests coming from the low-priority event group.

Each PaRAM contains two sections: the event entry table section and the transfer entry table section. An event entry describes an event type and associates the event to either one of transfer types or to an interrupt. In case an event entry associates the event to one of the transfer types, the event entry will contain a pointer to the specific transfer entry in the transfer entry table. The transfer table may contain up to eight transfer entries. A transfer entry specifies details required by the dMAX controller to perform the transfer. In case an event entry associates the event to an interrupt, the event entry specifies which interrupt should be generated to the CPU in case the event arrives.

Prior to enabling events and triggering a transfer, the event entry and transfer entry must be configured. The event entry must specify: type of transfer, transfer details (type of synchronization, reload, element size, etc.), and should include a pointer to the transfer entry. The transfer entry must specify: source, destination, counts, and indexes. If an event is sorted in the high-priority event group, the event entry and transfer entry must be specified in the high-priority Parameter RAM. If an event is sorted in the low-priority event group, the event entry and transfer entry must be specified in the low-priority parameter RAM.

The dMAX Event Flag Register (DEFR) captures up to 31 separate events; therefore, it is possible for events to occur simultaneously on the dMAX event inputs. In such cases, the event encoder resolves the order of processing. This mechanism sorts simultaneous events and sets the priority of the events. The dMAX controller can simultaneously process one event from each priority group. Therefore, the two highest-priority events (one from each group) can be processed at the same time.

An event-triggered dMAX transfer allows the submission of transfer requests to occur automatically based on system events, without any intervention by the CPU. The dMAX also includes support for CPU-initiated transfers for added control and robustness, and they can be used to start memory-to-memory transfers. To generate an event to the dMAX controller the CPU must create a transition on one of the bits from the dMAX Event Trigger (DETR) Register, which are mapped to the DER register.

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