Texas Instruments TMS320C6722, TMS320C6726, TMS320C6727 warranty

Contents

Main 1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs 1.1 Features 1.2 Description TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors 1.2.1 Device Compatibility 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the C672x device. Submit Documentation Feedback TMS320C6727, TMS320C6726, TMS320C6722 DSPs 5 A. UHPI is available only on the C6727. McASP2 is not available on the C6722. Figure 1-1. C672x DSP Block Diagram TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors 2 Device Overview 2.1 Device Characteristics TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors 2.2 Enhanced C67x+ CPU 2.3 CPU Interrupt Assignments Table 2-2. New Floating-Point Instructions for C67x+ CPU 2.4 Internal Program/Data ROM and RAM Figure 2-2. Program/Data ROM Organization 2.5 Program Cache 2.6 High-Performance Crossbar Switch Page Page 2.7 Memory Map Summary 2.8 Boot Modes Page Page 2.9 Pin Assignments 2.9.1 Pin Maps Submit Documentation Feedback Device Overview 19 Figure 2-8. 256-Terminal Ball Grid Array (GDH/ZDH Suffix)Bottom View TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors SPRS268E MAY 2005 REVISED JANUARY 2007 20 Device Overview Submit Documentation Feedback A. Actual size of Thermal Pad is 5.4 mm 5.4 mm. See Section 7.3 . Figure 2-9. 144-Pin Low-Profile Quad Flatpack (RFP Suffix)Top View 2.9.2 Terminal Functions TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors Page Page Page 2.10 Development 2.10.1 Development Support 2.10.2 Device Support TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors Submit Documentation Feedback Device Overview 27 Figure 2-10. TMS320C672x DSP Device Nomenclature Page Page 3 Device Configurations 3.1 Device Configuration Registers 3.2 Peripheral Pin Multiplexing Options 3.3 Peripheral Pin Multiplexing Control TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors Table 3-5. Priority of Control of Data Output on Multiplexed Pins 4 Peripheral and Electrical Specifications 4.1 Electrical Specifications 4.3 Recommended Operating Conditions 4.2 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) 4.4 Electrical Characteristics Over Operating Case Temperature Range (Unless Otherwise Noted) 4.5 Parameter Information 4.5.1 Parameter Information Device-Specific Information 4.6 Timing Parameter Symbology 4.7 Power Supplies 4.7.1 Power-Supply Sequencing 4.7.2 Power-Supply Decoupling 4.8 Reset 4.8.1 Reset Electrical Data/Timing Page dMAX Figure 4-4. dMAX Controller Block Diagram Page Page 4.9.2 dMAX Peripheral Registers Description(s) Table 4-3 is a list of the dMAX registers. Table 4-3. dMAX Configuration Registers Page 4.11 External Memory Interface (EMIF) 4.11.1 EMIF Device-Specific Information Figure 4-5. C6726/C6722 DSP 16-Bit EMIF Example Figure 4-6. C6727 DSP 32-Bit EMIF Example 4.11.2 EMIF Peripheral Registers Description(s) 4.11.3 EMIF Electrical Data/Timing Table 4-6. EMIF SDRAM Interface Switching Characteristics Table 4-7. EMIF Asynchronous Interface Timing Requirements Table 4-8. EMIF Asynchronous Interface Switching Characteristics Figure 4-7. Basic SDRAM Write Operation Figure 4-8. Basic SDRAM Read Operation Figure 4-9. Asynchronous Read WE Strobe Mode Figure 4-10. Asynchronous Read Select Strobe Mode Figure 4-11. Asynchronous Write WE Strobe Mode Figure 4-12. Asynchronous Write Select Strobe Mode Figure 4-13. EM_WAIT Timing Requirements 4.12 Universal Host-Port Interface (UHPI) [C6727 Only] 4.12.1 UHPI Device-Specific Information Figure 4-15. UHPI Multiplexed Host Address/Data Half-Word Mode Submit Documentation Feedback Peripheral and Electrical Specifications 57 Figure 4-16. UHPI Multiplexed Host Address/Data Fullword Mode 58 Peripheral and Electrical Specifications Submit Documentation Feedback Figure 4-17. UHPI Non-Multiplexed Host Address/Data Fullword Mode 4.12.2 UHPI Peripheral Registers Description(s) Table 4-11 is a list of the UHPI registers. Table 4-11. UHPI Configuration Registers Page Page 4.12.3 UHPI Electrical Data/Timing Table 4-16. UHPI Read and Write Switching Characteristics Figure 4-21. Non-Multiplexed Read/Write Timings Figure 4-22. Multiplexed Read Timings Using UHPI_HAS Figure 4-23. Multiplexed Read Timings With UHPI_HAS Held High TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors Figure 4-24. Multiplexed Write Timings With UHPI_HAS Held High 4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) Page 4.13.1 McASP Peripheral Registers Description(s) Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) TMS320C6727, TMS320C6726, TMS320C6722Floating-Point Digital Signal Processors Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued) Page Page Page 4.13.2 McASP Electrical Data/Timing Table 4-23. McASP Switching Characteristics Figure 4-29. McASP Input Timings Figure 4-30. McASP Output Timings Submit Documentation Feedback Peripheral and Electrical Specifications 79 4.14 Serial Peripheral Interface Ports (SPI0, SPI1) 4.14.1 SPI Device-Specific Information Figure 4-32. Illustration of SPI Master-to-SPI Slave Connection 4.14.2 SPI Peripheral Registers Description(s) Table 4-24 is a list of the SPI registers. Table 4-24. SPIx Configuration Registers 4.14.3 SPI Electrical Data/Timing Table 4-26. General Timing Requirements for SPIx Slave Modes Table 4-27. Additional SPI Master Timings, 4-Pin Enable Option SPI Master Timings, 4-Pin Chip Select Option Table 4-28. Additional Table 4-29. Additional SPI Master Timings, 5-Pin Option Table 4-30. Additional SPI Slave Timings, 4-Pin Enable Option SPI Slave Timings, 4-Pin Chip Select Option Table 4-31. Additional Table 4-32. Additional SPI Slave Timings, 5-Pin Option Figure 4-33. SPI TimingsMaster Mode Figure 4-34. SPI TimingsSlave Mode Figure 4-35. SPI TimingsMaster Mode (4-Pin and 5-Pin) Figure 4-36. SPI TimingsSlave Mode (4-Pin and 5-Pin) 4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) 4.15.1 I2C Device-Specific Information Figure 4-37. I2C Module Block Diagram 4.15.2 I2C Peripheral Registers Description(s) Table 4-33 is a list of the I2C registers. Table 4-33. I2Cx Configuration Registers 4.15.3 I2C Electrical Data/Timing Table 4-35. I2C Switching Characteristics Table 4-35. I2C Switching Characteristics (continued) Figure 4-38. I2C Receive Timings Figure 4-39. I2C Transmit Timings Page 4.16.2 RTI/Digital Watchdog Registers Description(s) Table 4-36. RTI Registers (continued) 4.17 External Clock Input From Oscillator or CLKIN Pin 4.17.1 Clock Electrical Data/Timing 4.18 Phase-Locked Loop (PLL) 4.18.1 PLL Device-Specific Information Figure 4-43. PLL Topology Table 4-40. Allowed PLL Operating Conditions at the board level through an external filter, asillustrated in Figure 4-44 . Figure 4-44. PLL Power Supply Filter 4.18.2 PLL Registers Description(s) 5 Application Example Submit Documentation Feedback Application Example 105 A. UHPI is only available on the C6727. McASP2 is not available on the C6722. Figure 5-1. TMS320C672x Audio DSP System Diagram 6 Revision History 7 Mechanical Data 7.1 Package Thermal Resistance Characteristics Table 7-2. Thermal Characteristics for RFP Package Page Page Page PACKAGING INFORMATION PACKAGE OPTION ADDENDUM Page Page IMPORTANT NOTICE