Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, Boot Modes

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

2.8 Boot Modes

The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the state of various device pins at reset, to determine which mode to enter. Note that in practice, only a few pins are used by the software.

CAUTION

Only an externally applied RESET causes the CFGPIN0 and CFGPIN1 registers to recapture their associated pin values. Neither an emulator reset nor a RTI reset causes these registers to update.

The ROM bootmodes include:

∙Parallel Flash on EM_CS[2]

∙SPI0 or I2C1 master mode from serial EEPROM

∙SPI0 or I2C1 slave mode from external MCU

∙UHPI from an external MCU

Table 2-9describes the required boot pin settings at device reset for each bootmode.

Table 2-9. Required Boot Pin Settings at Device Reset

BOOT MODE	UHPI_HCS	SPI0_SOMI	SPI0_SIMO	SPI0_CLK
UHPI	0	BYTEAD(1)	FULL(1)	NMUX(1)
Parallel Flash	1	0	1	0
SPI0 Master	1	0	0	1
SPI0 Slave	1	0	1	1
I2C1 Master	1	1	0	1
I2C1 Slave	1	1	1	1

(1)When UHPI_HCS is 0, the state of the SPI0_SOMI, SPI0_SIMO, and SPI0_CLK pins is copied into the specified bits in the CFGHPI register described in Table 4-12.

Refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual (literature number SPRS277) for details on supported bootmodes and their implementation.

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