Device Compatibility | Texas Instruments TMS320C6722, TMS320C6727

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:

∙Two 32-bit counter/prescaler pairs

∙Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)

∙Four compares with automatic update capability

∙Digital Watchdog (optional) for enhanced system robustness

Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN pin.

The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.

1.2.1 Device Compatibility

The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant enhancements including additional floating-point instructions. See Section 2.2

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TMS320C6727, TMS320C6726, TMS320C6722 DSPs

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Texas Instruments TMS320C6722, TMS320C6727, TMS320C6726 warranty Device Compatibility

Contents

Features TMS320C6727, TMS320C6726, TMS320C6722 DSPs Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance Characteristics Device Characteristics Characteristics of the C672x ProcessorsHardware Features C6726 Enhanced C67x+ CPU CPU Data Paths CPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves Operation Internal Program/Data ROM and RAM Byte Bank Cache Mode Program CacheProgram Cache Control Registers Register Name Byte Address Description High-Performance Crossbar Switch Block Diagram of Crossbar Switch Bus Bridges Label Bridge Description Master Clock Target Clock BIT no Name Reset Value Read Write Description Csprst C672x Memory Map Memory Map SummaryFfff Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLK BIT no Name Description PINCAP7 PINCAP15 Pin Assignments Pin Maps Pin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDH IO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2 Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP Package Development Support DevelopmentDevice Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ § Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing Options Options for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing Control Priority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third Priority Electrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 Unit Parameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CV Parameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX Unit Dual Data Movement Accelerator dMAX DMAX Device-Specific Information DMAX RAMREQ REQ RAM Submit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event Description DMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific Information Reset DSP EmifEmras Emwe Emcas EmclkEMWEDQM0 EMWEDQM1 Emif Peripheral Registers Descriptions Emif Registers Emif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX Unit Emif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1 Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672x DSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C 11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal Registers BIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENA BIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb Description Universal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO 17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins Comments Device-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal Registers Xclkchk XevtctlDITCSRA0 DITCSRA1 0x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 AMUTEIN1 Description AMUTEIN2 AMUTEIN2 Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B Serial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific Information Master SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P 29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information 15.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing Requirements Parameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal Registers Rtiintflag RtidwdctrlRtidwdprld Rtiwdstatus External Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator Components Clock Electrical Data/Timing 39. Clkin Timing Requirements Phase-Locked Loop PLL PLL Device-Specific Information Parameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMI PLL Registers Descriptions 41. PLL Controller Registers CODEC, DIR ADC, DAC, DSDSpio RTI ADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff Height PowerPAD PCB Footprint Packaging InformationPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice