Texas Instruments TMS320C6726, TMS320C6727, TMS320C6722 specification

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 3-5. Priority of Control of Data Output on Multiplexed Pins

PIN	FIRST PRIORITY	SECOND PRIORITY	THIRD PRIORITY
SPI0_SOMI/I2C0_SDA	SPI0_SOMI	I2C0_SDA
SPI0_CLK/I2C0_SCL	SPI0_CLK	I2C0_SCL
SPI0_SCS/I2C1_SCL	SPI0_SCS	I2C1_SCL
SPI0_ENA/I2C1_SDA	SPI0_ENA	I2C1_SDA
AXR0[5]/SPI1_SCS	AXR0[5]	SPI1_SCS
AXR0[6]/SPI1_ENA	AXR0[6]	SPI1_ENA
AXR0[7]/SPI1_CLK	AXR0[7]	SPI1_CLK
AXR0[8]/AXR1[5]/SPI1_SOMI	AXR0[8]	AXR1[5]	SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO	AXR0[9]	AXR1[4]	SPI1_SIMO
AXR0[10]/AXR1[3]	AXR0[10]	AXR1[3]
AXR0[11]/AXR1[2]	AXR0[11]	AXR1[2]
AXR0[12]/AXR1[1]	AXR0[12]	AXR1[1]
AXR0[13]/AXR1[0]	AXR0[13]	AXR1[0]
AXR0[14]/AXR2[1]	AXR0[14]	AXR2[1]
AXR0[15]/AXR2[0]	AXR0[15]	AXR2[0]
AHCLKR0/AHCLKR1	AHCLKR0	AHCLKR1
AHCLKX0/AHCLKX2	AHCLKX0	AHCLKX2
AMUTE2/HINT	AMUTE2	HINT
HD[16]/HHWIL	HD[16]	HHWIL
EM_D[31:16]/UHPI_HA[15:0](1)	EM_D[31:16] (Disabled if	UHPI_HA[15:0] (Input Only)
	CFGHPI.NMUX=1)

(1)When using the UHPI in non-multiplexed mode, ensure EM_D[31:16] are configured as inputs so that these pins may be used as UHPI_HA[15:0]. To ensure this, you must set the CFGHPI.NMUX bit to a '1'before the EMIF SDRAM initialization completes; otherwise, a drive conflict will occur. [The EMIF bus parking function drives the data bus in between accesses.]

32

Device Configurations

Submit Documentation Feedback

Image 32

Texas Instruments TMS320C6726, TMS320C6727, TMS320C6722 warranty Priority of Control of Data Output on Multiplexed Pins

Contents

Features TMS320C6727, TMS320C6726, TMS320C6722 DSPs Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance Characteristics Device Characteristics Characteristics of the C672x ProcessorsHardware Features C6726 Enhanced C67x+ CPU CPU Data Paths CPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves Operation Internal Program/Data ROM and RAM Byte Bank Cache Mode Program CacheProgram Cache Control Registers Register Name Byte Address Description High-Performance Crossbar Switch Block Diagram of Crossbar Switch Bus Bridges Label Bridge Description Master Clock Target Clock BIT no Name Reset Value Read Write Description Csprst Ffff Memory Map SummaryC672x Memory Map Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLK BIT no Name Description PINCAP7 PINCAP15 Pin Assignments Pin Maps Pin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDH IO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2 Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP Package Device Support DevelopmentDevelopment Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ § Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing Options Options for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing Control Priority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third Priority Electrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 Unit Parameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CV Tester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX Unit Dual Data Movement Accelerator dMAX DMAX Device-Specific Information DMAX RAMREQ REQ RAM Submit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event Description Byte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts External Memory Interface Emif Emif Device-Specific Information Reset DSP EmifEmras Emwe Emcas EmclkEMWEDQM0 EMWEDQM1 Emif Peripheral Registers Descriptions Emif Registers Emif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX Unit Emif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1 Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672x DSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C 11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal Registers BIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENA BIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb Description 15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO 17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins Comments Device-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal Registers Xclkchk XevtctlDITCSRA0 DITCSRA1 0x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 AMUTEIN1 Description AMUTEIN2 AMUTEIN2 22. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B Serial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific Information Slave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P 29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information Register Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing Requirements I2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal Registers Rtiintflag RtidwdctrlRtidwdprld Rtiwdstatus External Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator Components Clock Electrical Data/Timing 39. Clkin Timing Requirements Phase-Locked Loop PLL PLL Device-Specific Information Parameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMI PLL Registers Descriptions 41. PLL Controller Registers CODEC, DIR ADC, DAC, DSDSpio RTI ADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff Height PowerPAD PCB Footprint Packaging InformationPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice