Texas Instruments TMS320C6722 warranty McASP Electrical Data/Timing, McASP Timing Requirements1

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.13.2 McASP Electrical Data/Timing

4.13.2.1 Multichannel Audio Serial Port (McASP) Timing

Table 4-22and Table 4-23assume testing over recommended operating conditions (see Figure 4-29and Figure 4-30).

Table 4-22. McASP Timing Requirements(1) (2)

NO.			MIN	MAX UNIT
1	tc(AHCKRX)	Cycle time, AHCLKR external, AHCLKR input	20	ns
		Cycle time, AHCLKX external, AHCLKX input	20
2	tw(AHCKRX)	Pulse duration, AHCLKR external, AHCLKR input	7.5	ns
		Pulse duration, AHCLKX external, AHCLKX input	7.5
3	tc(ACKRX)	Cycle time, ACLKR external, ACLKR input	greater of 2P or 20 ns	ns
		Cycle time, ACLKX external, ACLKX input	greater of 2P or 20 ns
4	tw(ACKRX)	Pulse duration, ACLKR external, ACLKR input	10	ns
		Pulse duration, ACLKX external, ACLKX input	10
		Setup time, AFSR input to ACLKR internal	8
		Setup time, AFSX input to ACLKX internal	8
5	tsu(AFRXC-ACKRX)	Setup time, AFSR input to ACLKR external input	3	ns
		Setup time, AFSX input to ACLKX external input	3
		Setup time, AFSR input to ACLKR external output	3
		Setup time, AFSX input to ACLKX external output	3
		Hold time, AFSR input after ACLKR internal	0
		Hold time, AFSX input after ACLKX internal	0
6	th(ACKRX-AFRX)	Hold time, AFSR input after ACLKR external input	3	ns
		Hold time, AFSX input after ACLKX external input	3
		Hold time, AFSR input after ACLKR external output	3
		Hold time, AFSX input after ACLKX external output	3
		Setup time, AXRn input to ACLKR internal	8
7	tsu(AXR-ACKRX)	Setup time, AXRn input to ACLKR external input	3	ns
		Setup time, AXRn input to ACLKR external output	3
		Hold time, AXRn input after ACLKR internal	3
8	th(ACKRX-AXR)	Hold time, AXRn input after ACLKR external input	3	ns
		Hold time, AXRn input after ACLKR external output	3

(1)ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1 ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)P = SYSCLK2 period

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