Texas Instruments TMS320C6722, TMS320C6727 Additional1 SPI Master Timings, 4-Pin Enable Option2

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-27. Additional(1) SPI Master Timings, 4-Pin Enable Option(2) (3)

NO. MIN MAX UNIT

Delay from slave assertion of

17 td(ENA_SPC)M SPIx_ENA active to first SPIx_CLK from master.(4)

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

3P + 15

0.5tc(SPC)M + 3P + 15

ns

3P + 15

0.5tc(SPC)M + 3P + 15

Max delay for slave to deassert

SPIx_ENA after final SPIx_CLK

18 td(SPC_ENA)M edge to ensure master does not begin the next transfer.(5)

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

0.5tc(SPC)M

0

ns

0.5tc(SPC)M

0

(1)These parameters are in addition to the general timings for SPI master modes (Table 4-25).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)In the case where the master SPI is ready with new data before SPIx_ENA assertion.

(5)In the case where the master SPI is ready with new data before SPIx_ENA deassertion.

Table 4-28. Additional(1) SPI Master Timings, 4-Pin Chip Select Option(2) (3)

NO.

19td(SCS_SPC)M

20td(SPC_SCS)M

Delay from SPIx_SCS active to first SPIx_CLK(4)(5)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS(6)(7)

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

MIN MAX UNIT 2P – 10

0.5tc(SPC)M + 2P – 10

ns

2P – 10

0.5tc(SPC)M + 2P – 10

0.5tc(SPC)M

0

ns

0.5tc(SPC)M

0

(1)These parameters are in addition to the general timings for SPI master modes (Table 4-25).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)In the case where the master SPI is ready with new data before SPIx_SCS assertion.

(5)This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain asserted.

(7)This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

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