Texas Instruments TMS320C6722, TMS320C6727 warranty Additional1 SPI Slave Timings, 5-Pin Option2

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-32. Additional(1) SPI Slave Timings, 5-Pin Option(2) (3)

NO.

25td(SCSL_SPC)S

Required delay from SPIx_SCS asserted at slave to first SPIx_CLK edge at slave.

MIN	MAX UNIT
P	ns

26td(SPC_SCSH)S

Required delay from final SPIx_CLK edge before SPIx_SCS is deasserted.

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

0.5tc(SPC)M + P + 10

P + 10

ns

0.5tc(SPC)M + P + 10

P + 10

27tena(SCSL_SOMI)S

28tdis(SCSH_SOMI)S

29tena(SCSL_ENA)S

Delay from master asserting SPIx_SCS to slave driving SPIx_SOMI valid

Delay from master deasserting SPIx_SCS to slave 3-stating SPIx_SOMI

Delay from master deasserting SPIx_SCS to slave driving SPIx_ENA valid

P + 10	ns
P + 10	ns
15	ns

30tdis(SPC_ENA)S

Delay from final clock receive edge on SPIx_CLK to slave 3-stating or driving high SPIx_ENA.(4)

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK rising

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK falling

2P + 15

2P + 15

ns

2P + 15

2P + 15

(1)These parameters are in addition to the general timings for SPI slave modes (Table 4-26).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(4)SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is

3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.

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