High-Performance Crossbar Switch | Texas Instruments TMS320C6727

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

2.6 High-Performance Crossbar Switch

The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus masters and targets. Figure 2-4illustrates the connectivity of the crossbar switch.

ROM

RAM

CPU

Program

PLL

RTI

SPI0

SPI1

I2C0

I2C1

Cache

EMIF

Memory Controller

External

T2

Memory

Data

CPU

Program

SDRAM/

Flash

Master

Slave

Master

Peripheral Configuration Bus

Port

Port

Port

T3

(DMP)

(CSP)

(PMP)

Priority

M1

T1

M2

2

1

McASP0

McASP1

McASP2

BR1

BR2

BR3

BR4

SYSCLK1

SYSCLK1

SYSCLK3

SYSCLK3

McASP DMA Bus

SYSCLK2

SYSCLK2

SYSCLK1

SYSCLK2

T4

Priority

Priority

Priority

Priority

1

2

3

1

2

3

4

1

2

3

1

2

dMAX MAX0 Unit Master Port − High Priority

dMAX MAX1 Unit Master Port − Second Priority

Memory Controller DMP − Data Read/W rite by CPU

UHPI Master Interface (External Host CPU)

1

2

3

Crossbar

Priority

M5

External

UHPI

Config

M3

M4

T5

Host MCU

Universal Host-Port

MAX0

MAX1

Config

Interface

dMAX

Figure 2-4. Block Diagram of Crossbar Switch

As shown in Figure 2-4, there are five bus masters:

M1	Memory controller DMP for CPU data accesses to peripherals and EMIF.
M2	Memory controller PMP for program cache fills from the EMIF.
M3	dMAX HiMAX master port for high-priority DMA accesses.
M4	dMAX LoMAX master port for lower-priority DMA accesses.
M5	UHPI master port for an external MCU to access on-chip and off-chip memories.

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Texas Instruments TMS320C6727, TMS320C6722, TMS320C6726 High-Performance Crossbar Switch, Block Diagram of Crossbar Switch

Contents

Features TMS320C6727, TMS320C6726, TMS320C6722 DSPs Description Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance Characteristics Device Characteristics Characteristics of the C672x ProcessorsHardware Features C6726 Enhanced C67x+ CPU CPU Data Paths CPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves Operation Internal Program/Data ROM and RAM Byte Bank Cache Mode Program CacheProgram Cache Control Registers Register Name Byte Address Description High-Performance Crossbar Switch Block Diagram of Crossbar Switch Bus Bridges Label Bridge Description Master Clock Target Clock BIT no Name Reset Value Read Write Description Csprst Memory Map Summary C672x Memory MapFfff Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLK BIT no Name Description PINCAP7 PINCAP15 Pin Assignments Pin Maps Pin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDH IO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2 Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP Package Development Development SupportDevice Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ § Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing Options Options for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing Control Priority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third Priority Electrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 Unit Parameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CV Parameter Information Parameter Information Device-Specific InformationTester Pin Electronics Timing Parameter Symbology Power Supplies Power-Supply SequencingPower-Supply Decoupling Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX Unit Dual Data Movement Accelerator dMAX DMAX Device-Specific Information DMAX RAMREQ REQ RAM Submit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event Description DMAX Configuration Registers DMAX Peripheral Registers DescriptionsByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific Information Reset DSP EmifEmras Emwe Emcas EmclkEMWEDQM0 EMWEDQM1 Emif Peripheral Registers Descriptions Emif Registers Emif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX Unit Emif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1 Basic Sdram Write Operation Emclk Emras Emcas EmweBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode 11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode 13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672x DSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT 16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D 17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C 11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal Registers BIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENA BIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb Description Uhpi Electrical Data/Timing Universal Host-Port Interface Uhpi Read and Write Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 UHPIHDSx Read Write UHPIHA150Valid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO 17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins Comments Device-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal Registers Xclkchk XevtctlDITCSRA0 DITCSRA1 0x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 313 ReservedAMUTEIN0 Description AMUTEIN1 AMUTEIN1 Description AMUTEIN2 AMUTEIN2 McASP Electrical Data/Timing Multichannel Audio Serial Port McASP Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B Serial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific Information SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO Master SPISlave SPI 24. SPIx Configuration Registers SPI Peripheral Registers DescriptionsSPI0 SPI1 Register Name Description Byte Address SPI Electrical Data/Timing Serial Peripheral Interface SPI Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P 29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 32. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information 33. I2Cx Configuration Registers 15.2 I2C Peripheral Registers DescriptionsRegister Name Description Byte Address 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing Requirements 35. I2C Switching Characteristics ParameterI2CxSDA I2CxSCL Stop Start Repeated Real-Time Interrupt RTI Timer With Digital Watchdog 16.1 RTI/Digital Watchdog Device-Specific InformationWatchdog Key Register Bit Key RTI Interrupt Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal Registers Rtiintflag RtidwdctrlRtidwdprld Rtiwdstatus External Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator Components Clock Electrical Data/Timing 39. Clkin Timing Requirements Phase-Locked Loop PLL PLL Device-Specific Information Parameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMI PLL Registers Descriptions 41. PLL Controller Registers CODEC, DIR ADC, DAC, DSDSpio RTI ADDS/CHANGES/DELETES Package Thermal Resistance Characteristics Thermal Characteristics for GDH/ZDH PackageThermal Characteristics for RFP Package Standoff Height Standoff Height PowerPAD PCB Footprint Packaging InformationPage Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Page Important Notice