Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, rising

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-7. EMIF Asynchronous Interface Timing Requirements(1) (2)

NO.

28tsu(EM_DV-EM_CLKH)A

29th(EM_CLKH-EM_DIV)A

30tsu(EM_CLKH-EM_WAITV)A

31th(EM_CLKH-EM_WAITIV)A

33tw(EM_WAIT)A

34td(EM_WAITD-HOLD)A

35tsu(EM_WAITA-HOLD)A

	MIN	MAX	UNIT
Input setup time, read data valid on EM_D[31:0] before EM_CLK	5		ns
rising
Input hold time, read data valid on EM_D[31:0] after EM_CLK rising	2		ns
Setup time, EM_WAIT valid before EM_CLK rising edge	5		ns
Hold time, EM_WAIT valid after EM_CLK rising edge	0		ns
Pulse width of EM_WAIT assertion and deassertion	2E + 5		ns
Delay from EM_WAIT sampled deasserted on EM_CLK rising to		4E(3)	ns
beginning of HOLD phase
Setup before end of STROBE phase (if no extended wait states are	4E(3)
inserted) by which EM_WAIT must be sampled asserted on			ns
EM_CLK rising in order to add extended wait states.(4)

(1)E = SYSCLK3 (EM_CLK) period.

(2)These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

(3)These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge must also be met in order to ensure the EM_WAIT signal is correctly sampled.

(4)In Figure 4-13, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 4-8. EMIF Asynchronous Interface Switching Characteristics(1)

NO.		PARAMETER	MIN	MAX	UNIT
1	tc(EM_CLK)	Cycle time, EMIF clock EM_CLK	10		ns
2	tw(EM_CLK)	Pulse width, high or low, EMIF clock EM_CLK	3		ns
17	tdis(EM_CLKH-EM_DHZ)S	Delay time, EM_CLK rising to EM_D[31:0] 3-stated		7.7	ns
18	tena(EM_CLKH-EM_DLZ)S	Output hold time, EM_CLK rising to EM_D[31:0] driving	1.15		ns
21	td(EM_CLKH-EM_CS2V)A	Delay time, from EM_CLK rising edge to EM_CS[2] valid	0	8	ns
22	td(EM_CLKH-EM_WE_DQMV)A	Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid	0	8	ns
23	td(EM_CLKH-EM_AV)A	Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid	0	8	ns
24	td(EM_CLKH-EM_DV)A	Delay time, EM_CLK rising to EM_D[31:0] valid	0	8	ns
25	td(EM_CLKH-EM_OEV)A	Delay time, EM_CLK rising to EM_OE valid	0	8	ns
26	td(EM_CLKH-EM_RW)A	Delay time, EM_CLK rising to EM_RW valid	0	8	ns
27	tdis(EM_CLKH-EM_DDIS)A	Delay time, EM_CLK rising to EM_D[31:0] 3-stated	0	8	ns
32	td(EM_CLKH-EM_WE)A	Delay time, EM_CLK rising to EM_WE valid	0	8	ns

(1)These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

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