Texas Instruments TMS320C6722, TMS320C6727, TMS320C6726 Floating-PointDigital Signal Processors

	TMS320C6727, TMS320C6726, TMS320C6722
www.ti.com	Floating-Point Digital Signal Processors
	SPRS268E –MAY 2005 –REVISED JANUARY 2007
31	8
	Reserved
7	0
	HPIAMSB

R/W, 0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C)

Table 4-13. CFGHPIAMSB Register Bit Field Description (0x4000 000C)

BIT NO.	NAME	RESET	READ
		VALUE	WRITE
31:8	Reserved	N/A	N/A
7:0	HPIAMSB	0	R/W

DESCRIPTION

Reads are indeterminate. Only 0s should be written to these bits.

UHPI most significant byte of DSP address to access in Non-Multiplexed mode and in Multiplexed Address and Data mode when PAGEM = 1. Sets bits [31:24] of the DSP internal address as accessed through UHPI.

31	8
	Reserved
7	0
	HPIAUMB

R/W, 0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 4-20. CFGHPIAUMB Register Bit Layout (0x4000 0010)

Table 4-14. CFGHPIAUMB Register Bit Field Description (0x4000 0010)

BIT NO.	NAME	RESET	READ
		VALUE	WRITE
31:8	Reserved	N/A	N/A
7:0	HPIAUMB	0	R/W

DESCRIPTION

Reads are indeterminate. Only 0s should be written to these bits.

UHPI upper middle byte of DSP address to access in Non-Multiplexed mode and in Multiplexed Address and Data mode when PAGEM = 1. Sets bits [23:16] of the DSP internal address as accessed through UHPI.

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