Texas Instruments TMS320C6726, TMS320C6727 warranty Additional1 SPI Master Timings, 5-Pin Option2

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-29. Additional(1) SPI Master Timings, 5-Pin Option(2) (3)

NO.

18td(SPC_ENA)M

20td(SPC_SCS)M

Max delay for slave to deassert SPIx_ENA after final SPIx_CLK edge to ensure master does not begin the next transfer.(4)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS(5)(6)

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

MIN	MAX UNIT
	0.5tc(SPC)M
	0
	ns
	0.5tc(SPC)M
	0
0.5tc(SPC)M
0
	ns
0.5tc(SPC)M
0

21td(SCSL_ENAL)M

Max delay for slave SPI to drive SPIx_ENA valid after master asserts SPIx_SCS to delay the master from beginning the next transfer.

0.5P ns

22td(SCS_SPC)M

23td(ENA_SPC)M

Delay from SPIx_SCS active to first SPIx_CLK(7)(8)(9)

Delay from assertion of SPIx_ENA low to first SPIx_CLK edge.(10)

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

2P	– 10
0.5tc(SPC)M + 2P	– 10
	ns
2P	– 10
0.5tc(SPC)M + 2P	– 10
	3P + 15
	0.5tc(SPC)M + 3P + 15
	ns
	3P + 15
	0.5tc(SPC)M + 3P + 15

(1)These parameters are in addition to the general timings for SPI master modes (Table 4-25).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)In the case where the master SPI is ready with new data before SPIx_ENA deassertion.

(5)Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain asserted.

(6)This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(7)If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx_ENA.

(8)In the case where the master SPI is ready with new data before SPIx_SCS assertion.

(9)This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(10)If SPIx_ENA was initially deasserted high and SPIx_CLK is delayed.

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