Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.13.1 McASP Peripheral Registers Description(s)

Table 4-18is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU878).

Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus

	McASP0	McASP1	McASP2	REGISTER
	BYTE	BYTE	BYTE		DESCRIPTION
				NAME
	ADDRESS	ADDRESS	ADDRESS
			Device-Level Configuration Registers Controlling McASP
	0x4000 0018	0x4000 001C	0x4000 0020	CFGMCASPx	Selects the peripheral pin to be used as AMUTEINx
				McASP Internal Registers
	0x4400 0000	0x4500 0000	0x4600 0000	PID	Peripheral identification register
	0x4400 0004	0x4500 0004	0x4600 0004	PWRDEMU	Power down and emulation management register
	0x4400 0010	0x4500 0010	0x4600 0010	PFUNC	Pin function register
	0x4400 0014	0x4500 0014	0x4600 0014	PDIR	Pin direction register
	0x4400 0018	0x4500 0018	0x4600 0018	PDOUT	Pin data output register
	0x4400 001C	0x4500 001C	0x4600 001C	PDIN (reads)	Read returns: Pin data input register
				PDSET (writes)	Writes affect: Pin data set register
					(alternate write address: PDOUT)
	0x4400 0020	0x4500 0020	0x4600 0020	PDCLR	Pin data clear register (alternate write address: PDOUT)
	0x4400 0044	0x4500 0044	0x4600 0044	GBLCTL	Global control register
	0x4400 0048	0x4500 0048	0x4600 0048	AMUTE	Audio mute control register
	0x4400 004C	0x4500 004C	0x4600 004C	DLBCTL	Digital loopback control register
	0x4400 0050	0x4500 0050	0x4600 0050	DITCTL	DIT mode control register
	0x4400 0060	0x4500 0060	0x4600 0060	RGBLCTL	Receiver global control register: Alias of GBLCTL, only
					receive bits are affected - allows receiver to be reset
					independently from transmitter
	0x4400 0064	0x4500 0064	0x4600 0064	RMASK	Receive format unit bit mask register
	0x4400 0068	0x4500 0068	0x4600 0068	RFMT	Receive bit stream format register
	0x4400 006C	0x4500 006C	0x4600 006C	AFSRCTL	Receive frame sync control register
	0x4400 0070	0x4500 0070	0x4600 0070	ACLKRCTL	Receive clock control register
	0x4400 0074	0x4500 0074	0x4600 0074	AHCLKRCTL	Receive high-frequency clock control register
	0x4400 0078	0x4500 0078	0x4600 0078	RTDM	Receive TDM time slot 0-31 register
	0x4400 007C	0x4500 007C	0x4600 007C	RINTCTL	Receiver interrupt control register
	0x4400 0080	0x4500 0080	0x4600 0080	RSTAT	Receiver status register
	0x4400 0084	0x4500 0084	0x4600 0084	RSLOT	Current receive TDM time slot register
	0x4400 0088	0x4500 0088	0x4600 0088	RCLKCHK	Receive clock check control register
	0x4400 008C	0x4500 008C	0x4600 008C	REVTCTL	Receiver DMA event control register
	0x4400 00A0	0x4500 00A0	0x4600 00A0	XGBLCTL	Transmitter global control register. Alias of GBLCTL, only
					transmit bits are affected - allows transmitter to be reset
					independently from receiver
	0x4400 00A4	0x4500 00A4	0x4600 00A4	XMASK	Transmit format unit bit mask register
	0x4400 00A8	0x4500 00A8	0x4600 00A8	XFMT	Transmit bit stream format register
	0x4400 00AC	0x4500 00AC	0x4600 00AC	AFSXCTL	Transmit frame sync control register
	0x4400 00B0	0x4500 00B0	0x4600 00B0	ACLKXCTL	Transmit clock control register
	0x4400 00B4	0x4500 00B4	0x4600 00B4	AHCLKXCTL	Transmit high-frequency clock control register
	0x4400 00B8	0x4500 00B8	0x4600 00B8	XTDM	Transmit TDM time slot 0-31 register
	0x4400 00BC	0x4500 00BC	0x4600 00BC	XINTCTL	Transmitter interrupt control register
	0x4400 00C0	0x4500 00C0	0x4600 00C0	XSTAT	Transmitter status register
	0x4400 00C4	0x4500 00C4	0x4600 00C4	XSLOT	Current transmit TDM time slot register
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