Epson S1D13504 MD Configuration Readback Register, Gpio Configuration Register, MD9 MD8, Status

Epson Research and Development	Page 103
Vancouver Design Center

bit 0	Half Frame Buffer Disable
	This bit is used to disable the Half Frame Buffer.
	When this bit = 1, the Half Frame Buffer is disabled. When this bit = 0, the Half Frame Buffer is
	enabled. When a single panel is selected, the Half Frame Buffer is automatically disabled and this
	bit has no hardware effect.
	The Half Frame Buffer is needed to fully support dual panels. Disabling the Half Frame Buffer
	reduces memory bandwidth requirements and increases the supportable pixel clock frequency, but
	results in reduced contrast on the LCD panel. This mode is not normally used except in special
	circumstances such as simultaneous display on a CRT and dual panel LCD. See Section 11.2 on
	page 120 for details.

Note

The Half Frame Buffer should be disabled only when idle. The Half Frame Buffer is idle during vertical non-display periods (i.e. when REG[0Ah] bit 7 = 1), or while in suspend mode. For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

MD Configuration Readback Register 0

REG[1Ch]							RO
MD7 Status	MD6 Status	MD5 Status	MD4 Status	MD3 Status	MD2 Status	MD1 Status	MD0 Status

MD Configuration Readback Register 1

REG[1Dh]							RO
MD15	MD14	MD13	MD12	MD11	MD10	MD9	MD8
Status	Status	Status	Status	Status	Status	Status	Status

REG[1Ch] bits 7-0 MD[15:0] Configuration Status

REG[1Dh] bits 7-0 These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of RESET#.

See Table 5-8: “Summary of Power On / Reset Options,” on page 31.

GPIO Configuration Register 0
REG[1Eh]							RW
GPIO7 Pin	GPIO6 Pin	GPIO5 Pin	GPIO4 Pin	GPIO3 Pin	GPIO2 Pin	GPIO1 Pin	GPIO0 Pin
IO Config.	IO Config.	IO Config.	IO Config.	IO Config.	IO Config.	IO Config.	IO Config.
bit 7	GPIO7 Pin IO Configuration
	When this bit = 1, GPIO7 is configured as an output. When this bit = 0 (default), GPIO7 is config-
	ured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7,
	otherwise the DACWR# pin is controlled automatically and this bit will have no effect on hard-
	ware.
bit 6	GPIO6 Pin IO Configuration
	When this bit = 1, GPIO6 is configured as an output. When this bit = 0 (default), GPIO6 is config-
	ured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6,
	otherwise the DACP0 pin is controlled automatically and this bit will have no effect on hardware.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18