Epson S1D13504 manual Split Screen, REG0E Screen 1 Line Compare Register, Line Compare Bit

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4.3 Split Screen

Occasionally the need arises to display two distinct images on the display. For example, we may want to write a game where the main play area will be rapidly updated and we want an unchanging status display at the bottom of the screen.

The Split Screen feature of the S1D13504 allows a programmer to set up a display for such an appli- cation. The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239. Although this example picks specific values, image 1 and image 2 can be shown as varying portions of the screen.

Scan Line 0

...

Scan Line 99

Scan Line 100

Image 1

...

Image 2

Scan Line 239

Screen 1 Display Line Count Register = 99 lines

Figure 4-2: 320x240 Single Panel For Split Screen

4.3.1 Registers

The other registers required for split screen operations, [10h] through [12h] (Screen 1 Display Start Address) and [18h] (Pixel Panning Register), are described in section 4.2.1 on page 26.

REG[0E] Screen 1 Line Compare Register 0

Line Compare	Line Compare	Line Compare	Line Compare	Line Compare	Line Compare	Line Compare	Line Compare
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[0F] Screen 1 Line Compare Register 1
n/a	n/a	n/a	n/a	n/a	n/a	Line Compare	Line Compare
						Bit 9	Bit 8

These two registers form a value known as the line compare. When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display. When the line compare value is less than the number of physically displayed lines, display operation works like this:

1.From the end of vertical non-display to the number of lines indicated by line compare the dis- play data will be from the memory pointed to by the Screen 1 Display Start Address.

2.After line compare lines have been displayed the display will begin showing data from Screen 2 Display Start Address memory.

S1D13504	Programming Notes and Examples
X19A-G-002-07	Issue Date: 01/02/01