Epson S1D13504 LCD Power Sequencing and Power Save Modes, Introduction to LCD Power Sequencing

Page 30	Epson Research and Development
	Vancouver Design Center

5 LCD Power Sequencing and Power Save Modes

5.1 Introduction to LCD Power Sequencing

LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals. Power sequencing is required to prevent long term damage to the panel and to avoid unsightly “lines” on power down and start-up.

LCD Power Sequencing is performed on the S1D13504 through a software procedure even when using hardware power save modes. Most “green” systems today use some sort of software power down procedure in conjunction with external circuitry to set hardware suspend modes. These proce- dures typically save/restore state information, or provide a timer prior to initiating power down. The S1D13504 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down. Conversely, the LCD signals must be active prior to the power supply starting up. For simplicity, we have chosen to use the same time value for power up and power down proce- dures.

The time interval required varies depending on the power supply design. The power supply on the S5U13504B00C Evaluation board requires 0.5 seconds to fully discharge. Your power supply design may vary.

Below are the procedures for all cases in which power sequencing is required.

5.2 Introduction to Power Save Modes

The S1D13504 has two power save modes. One is hardware-initiated via the SUSPEND# pin, the other is software-initiated through REG[1A] bit 0. Both require power sequencing as described above.

5.3 Registers

Register bits discussed in this section are highlighted.

Display Mode Register

REG[0D]

	Simultaneous	Simultaneous	Number of	Number of	Number of
n/a	Display	Display	BPP Select	BPP Select	BPP Select	CRT Enable	LCD Enable
	Option Select	Option Select
			Bit 2	Bit 1	Bit 0
	Bit 1	Bit 0
Power Save Configuration Register
REG[1A]
				LCD Power	Suspend	Suspend	Software
n/a	n/a	n/a	n/a		Refresh	Refresh	Suspend
				Disable
					Select Bit 1	Select Bit 0	Mode Enable

Suspend Refresh Select bits [1:0] should be set on power up depending on the type of DRAM available. See the Hardware Functional Specification, document number X19A-A-002-xx.

S1D13504	Programming Notes and Examples
X19A-G-002-07	Issue Date: 01/02/01