Technical Manual
Document Number X19A-Q-002-14
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Customer Support Information
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Power Down Modes
General Purpose IO pins
Memory Interface
CPU Interface
CPU
Ramdac
Hardware Functional Specification
Document Number X19A-A-002-18
X19A-A-002-18 Issue Date 01/01/30
Table of Contents
Registers
Display Configuration 116
Power Save Modes 128
Display Buffer
Clocking 119
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List of Tables
Vancouver Design Center
List of Figures
Vancouver Design Center
Scope
Introduction
Overview Description
Features
Memory Interface
CPU Interface
Display Support
Display Modes
Clock Source
Miscellaneous
Package and Pin
Typical System Implementation Diagrams
LCD
Management MC68000
Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM
Functional Block Diagram
Block Description
Functional Block Descriptions Host Interface
Memory Controller
Look-Up Table
Power Save
LCD Interface
Pin Out
Pinout Diagram for S1D13504F00A
Package type 128 pin surface mount QFP15
Pinout Diagram for S1D13504F01A
Package type 128 pin surface mount TQFP15
Pinout Diagram for S1D13504F02A
Package type 144 pin surface mount QFP20
Pin Description
Key
AB0
TS2
CS#
Busclk
BS#
RD/WR#
RESET#
WAIT# TS2
LCAS# CO1
UCAS# CO1
WE# CO1
RAS# CO1
MA9 TS1
Clock Input
LCD Interface Pin Descriptions
CRT and External Ramdac Interface
CRT and Ramdac Interface Pin Descriptions
Hrtc
Vrtc
BLANK# CN3
Power Supply
Pin # Pin Name Type Driver Description F00A F02A F01A
Summary of Configuration Options
Multiple Function Pin Mapping
S1D13504 SH-3 MC68K Bus Generic MPU Pin Names
Asym 256Kx16
Asym 1Mx16
11 LCD, CRT, Ramdac Interface Pin Mapping
Symbol Parameter Rating Units
C. Characteristics
Symbol Parameter Condition Min Typ Max Units
Low Level Output Voltage
Output Leakage Current
Output Pin Capacitance
Bidirectional Pin Capacitance
RD/WR# BS#
CPU Interface Timing 1 SH-3 Interface Timing
WAIT#
Symbol Parameter Min Max Units
AS# UDS# LDS#
2 MC68K Bus 1 Interface Timing e.g. MC68000
T13 T14 T15 D150read
AS# high setup to CLK
AS# high to DTACK# high impedance
D150 hold from falling edge of DTACK# write cycle
D150 valid to DTACK# falling edge read cycle
3 MC68K Bus 2 Interface Timing e.g. MC68030
A200 SIZ10 M/R#
AS# DS#
T13 T14 T15
D3116 hold from falling edge of DSACK1# write cycle
D3116 valid to DSACK1# falling edge read cycle
Generic MPU Interface Synchronous Timing
Bclk
A200
RD0#,RD1# WE0#,WE1# Hi-Z
Low write cycle D150 hold from WE0#, WE1# high write cycle
A200 Valid
Generic MPU Interface Asynchronous Timing
Hi-Z Valid T10 D150read
T82
Symbol Parameter Min Typ Max Units
Clock Input Requirements
Memory Interface Timing EDO-DRAM Read Timing
RAS# CAS#
EDO Dram Read Timing
EDO-DRAM Write Timing
RAS# CAS# WE#
T14 Write Data setup time 45 t1 T15 Write Data hold time
55 t1 + CAS# precharge time 45 t1
EDO-DRAM Read-Write Timing
EDO-DRAM Read-Write Timing
EDO Dram Read-Write Timing
EDO-DRAM CAS Before RAS Refresh Timing
10 EDO-DRAM CAS Before RAS Refresh Timing
EDO-DRAM Self-Refresh Timing
11 EDO-DRAM Self-Refresh Timing
FPM-DRAM Read Timing
12 FPM-DRAM Read Timing
12 FPM Dram Read Timing
FPM-DRAM Write Timing
13 FPM-DRAM Write Timing
T14 Write Data setup time 45 t1 T15 Write Data hold time
FPM-DRAM Read-Write Timing
14 FPM-DRAM Read-Write Timing
45 t1 S1D13504
FPM-DRAM CAS# Before RAS# Refresh Timing
RAS# precharge time REG22h bits 32 = 01 or 45 t1
FPM-DRAM Self-Refresh Timing
16 FPM-DRAM CBR Self-Refresh Timing
Display Interface Power-On/Reset Timing
Fpframe active
Suspend Timing
Mclk
Single Monochrome 4-Bit Panel Timing
VDP =
Vndp =
HDP =
Sync Timing
Data Timing
Single Monochrome 8-Bit Panel Timing
VDP
Vndp
HDP
UD30, LD30 setup to Fpshift falling edge
UD30, LD30 hold to Fpshift falling edge
= REG05h bits 40 + 1*8 23 Ts
= REG05h bits 40 + 1*8 14 Ts
Single Color 4-Bit Panel Timing
23 Single Color 4-Bit Panel Timing
= REG05h bits 40 + 1*8 26 Ts
= REG04h bits 60+1*8 1 Ts
= REG05h bits 40 + 1*8 17 Ts
Single Color 8-Bit Panel Timing Format
25 Single Color 8-Bit Panel Timing Format
UD30, LD30 setup to FPSHIFT2 rising, Fpshift falling edge
Fpline pulse width Fpline period
FPSHIFT2 falling edge to Fpline rising edge
FPSHIFT2, Fpshift pulse width high
27 Single Color 8-Bit Panel Timing Format
T1min = t3min 9Ts
Single Color 16-Bit Panel Timing
VDP Vndp LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP Hndp
UD70, LD70 setup to Fpshift falling edge
UD70, LD70 hold to Fpshift falling edge
Dual Monochrome 8-Bit Panel Timing
Fpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
= REG05h bits 40 + 1*8 8 Ts
Dual Color 8-Bit Panel Timing
33 Dual Color 8-Bit Panel Timing
= REG05h bits 40 + 1*8 9 Ts
Dual Color 16-Bit Panel Timing
35 Dual Color 16-Bit Panel Timing
UD70 LD70
12 16-Bit TFT Panel Timing
= Vertical Display Period = REG09h bits 10, REG08h bits 70 +
38 TFT A.C. Timing
= REG07h bits 30+1*8 Ts
= REG04h bits 60+1*8 + REG05h bits 40+1*8 Ts
= REG0Ch bits 20+1 lines
CRT Timing
39 CRT Timing
40 CRT A.C. Timing
Dacclk period
External Ramdac Read / Write Timing
Read
Write
DACWR# pulse width low
Registers
Register Mapping
Register Descriptions
Revision Code Register
Memory Configuration Register
Memory Configuration Registers
Time/256 Cycles
Panel/Monitor Configuration Registers
Panel Type Register
MOD Rate Register
REG03h MOD Rate Bit
Horizontal Non-Display Period Register
Horizontal Display Width Register
HRTC/FPLINE Start Position Register
Vertical Display Height Register
HRTC/FPLINE Pulse Width Register
Hrtc Fpline
VRTC/FPFRAME Start Position Register
Vertical Non-Display Period Register
Vrtc Fpframe
VRTC/FPFRAME Pulse Width Register
REG0Ch
Fpframe Vrtc
Vrtc Polarity
Display Configuration Registers
Display Mode Register
Simultaneous Display Option Select Bits
Even Scan Only
Number of Bits-Per-Pixel Selection
Screen 1 Line Compare Register
Screen 1 Display Start Address Register
Screen 2 Display Start Address Register
Screen 2 Display Start Address Register 0 RW
Memory Address Offset Register
Clock Configuration Register
Clock Configuration Register
Pixel Panning Register
Number of Bits-Per-Pixel Screen 2 Pixel Panning Bits Used
Power Save Configuration Registers
Power Save Configuration Register
Miscellaneous Disable Register
Miscellaneous Registers
MD Configuration Readback Register
Gpio Configuration Register
REG1Dh MD15 MD14 MD13 MD12 MD11 MD10
MD9 MD8
Vancouver Design Center
REG1Fh GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config
Gpio Status / Control Register
Gpio Status / Control Register
REG21h
GPO
GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin Control IO Status
Performance Enhancement Register
REG22h EDO Read RC Timing RAS# to
REG22h Bits
Minimum Random Cycle Width t RC
RAS# to CAS# Delay tRCD
Optimal Dram Timing
REG22h Bit
RAS# Precharge Width t RP
Look-Up Table Registers
RGB Index Bits Look-Up Table Access Pointer Sequence
Look-Up Table Address Register
Look-Up Table Data Register
Look-Up Table Bank Select Register
REG26h LUT Data Bit
REG27h Red Bank Blue Bank Green Bank Select Bit
Ramdac Read Mode Address Register
Ramdac Write Mode Address Register
External Ramdac Control Registers
Ramdac Pixel Read Mask Register
Ramdac Palette Data Register
REG2Eh or REG2Fh
Display Buffer
512K byte Memory AB200
Image Buffer
Half Frame Buffer
Display Configuration
Display Mode Data Format
15/16 Bit-Per-Pixel Format Memory Organization
Display
Image Manipulation
Image Buffer
Clocking
Maximum Mclk Pclk Ratios
Display type
Maximum Pclk Allowed Bpp 16 bpp
Frame Rate Calculation
= Pclk
Speed Grade Bpp Clock Hndpt s Panel
MHz
FPM-DRAM
Bit-Per-Pixel Mode
Display Mode Bit Wide Look-Up Table
Look-Up Table Architecture
Gray Shade Display Modes
Bit-Per-Pixel Mode
Bit-Per-Pixel Color Mode
Color Display Modes
Bank Selected Bank Entry Bit Red data output Logic
Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110
Color Data Format Red Look-Up Table
Hardware Suspend
Power Save Modes
Software Suspend
Power Save Mode Function Summary
Pin States in Power Save Modes
Power Save Mode PSM
Pin State Pins Normal Software Hardware Active Suspend
14.1 QFP15-128 S1D13504F00A
Mechanical Data
QFP15 128 pin Unit mm
TQFP15 128 pin Unit mm
TQFP15-128 S1D13504F01A
±0.2
QFP20 144 pin Unit mm
QFP20-144 S1D13504F02A
125
Programming Notes and Examples
Document Number X19A-G-002-07
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Introduction Programming the S1D13504 Registers
LCD Power Sequencing and Power Save Modes
Advanced Techniques
CRT Considerations
Identifying the S1D13504 Hardware Abstraction Layer HAL
Sample Code
Appendix a Supported Panel Values
Initializing the S1D13504 Registers
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Introduction
2 REG22 bits 7-2 Performance Enhancement Register
Programming the S1D13504 Registers
3 REG02 bit 1 Dual/Single Panel Type
5 REG23 Display Fifo
4 REG1B bit 0 Half Frame Buffer Disable
Register Initialization Initialization Sequence
Initializing the S1D13504 Registers
Initialization Example
Operation Description
Re-Programming Registers
Disabling the Half Frame Buffer Sequence
Bit
Display Buffer Location
Pixel Bit
Memory Organization for Eight Bit-per-pixel 256 Colors
Bit Red Bit Green Bit Blue Bit
Memory Organization for 16 Bit-per-pixel 65536 Colors
Memory Organization for 15 Bit-per-pixel 32768 Colors
Bit Reserved Red Bit Green Bit Blue Bit
Look-Up Table LUT
REG24h Look-Up Table Address Register Read/Write
REG26h Look-Up Table Data Register Read/Write
REG27h Look-Up Table Bank Register Read/Write
Bank Select Bits
Look-Up Table Organization
Look-Up Table Configurations
Bank
Recommended LUT Values for 1 bpp Color Mode
Recommended LUT Values for 2 bpp Color Mode
Color Modes
Address Red Green Blue
11 Recommended LUT Values For 8 bpp Color Mode
12 Examples of 256 Pixel Colors Using Linear LUT
Gray Shade Modes
13 Recommended LUT Values for 1 bpp Gray Shades
Pixel Value Color
15 Recommended LUT Values for 8 bpp Gray Shade
14 Recommended LUT Values for 2 bpp Gray Shades
LUT Address Green LUT Data
Bpp Gray Shade
Advanced Technique s
Virtual Display
Registers
Examples
REG16h Memory Address Offset Register
REG17h Memory Address Offset Register
Panning and Scrolling
Number of Pixels Panned Using Start Address
Active Pixel Pan Bits
Example 4 Panning Right and Left
Split Screen
REG0E Screen 1 Line Compare Register
Line Compare Bit
REG0F Screen 1 Line Compare Register
REG14h Screen 2 Display Start Address Register
REG13h Screen 2 Display Start Address Register
REG15h Screen 2 Display Start Address Register
LCD Power Sequencing and Power Save Modes
Introduction to LCD Power Sequencing
Introduction to Power Save Modes
Display Mode Register
Suspend Enable Sequence
Shortening the 128 Frame delay using Software Suspend
Shortening the 128 Frame Delay using Hardware SUSPEND#
Suspend Sequencing
Suspend Disable Sequence
LCD Enable/Disable Sequencing Reg0D bit
LCD Enable / Disable using Power Save Modes
LCD Enable / Disable using Manual Control
CRT Considerations
Introduction
CRT Only
Ramdac Register Mapping for Little/Big-Endian
Simultaneous Display
Related Register Data for CRT Only
Address
Address
Related register data for Simultaneous Display
Register 640X480@75Hz 640X480@60Hz
Identifying the S1D13504
API for 13504HAL
Hardware Abstraction Layer HAL
Initialization Int seDeRegisterDeviceint device
Int seGetIdint device, Byte *pId
Int seInitHalvoid
Int seValidRegisteredDeviceint device
Int seSetInitint device
Int seValidStdDeviceint device
Int seGetBitsPerPixelint device, Byte *pBitsPerPixel
Int seGetBytesPerScanlineint device, int *pBytes
Int seGetLastUsableByteint device, Dword *pLastByte
Int seGetLinearDispAddrint device, Dword *pDispLogicalAddr
Int seReadDisplayByteint device, Dword offset, Byte *pByte
Int seGetScreenSizeint device, int *width, int *height
Int seReadDisplayWordint device, Dword offset, Word *pWord
Int seSetBitsPerPixelint device, Byte BitsPerPixel
Int seSplitInitint device, Dword Scrn1Addr, Dword Scrn2Addr
Int seVirtInitint device, int xVirt, long *yVirt
Int seVirtMoveint device, Byte WhichScreen, int x, int y
Vancouver Design Center
Int seGetDacEntryint device, Byte index, Byte *pEntry
Color Manipulation Int seGetDacint device, Byte *pDac
Int seGetLutint device, Byte *pLut
Int seSetDacint device, Byte *pDac
Int seGetLutEntryint device, Byte index, Byte *pEntry
Int seSetDacEntryint device, Byte index, Byte *pEntry
Int seSetLutint device, Byte *pLut
Int seSetLutEntryint device, Byte index, Byte *pEntry
Int seDrawTextint device, char *fmt
Int sePutcharint ch
Int seGetcharvoid
Int sePutcint device, int ch
Int seSetPixelint device, int x, int y, Dword color
Miscellaneous Int seDelayint device, Dword Seconds
Int seSetRegint device, int index, Byte val
Word seRotateByteLeftBYTE val, Byte bits
Word seRotateByteRightBYTE val, Byte bits
Sample code using 13504HAL API
Sample Code
Sample code without using 13504HAL API
Vancouver Design Center
Pclk
To arrive at the frame rate closest to the desired
Words
Fifo
Appendix a Supported Panel Values
Supported Panel Values
Passive Single Panel
Passive Dual Panel
TFT Panel
TFT 16-Bit Register Single
01/02/02
Number of Bits/Pixel
13504CFG.EXE Configuration Program
Document Number X19A-B-001-04
Vancouver Design Center
X19A-B-001-04
Script Mode Interactive Mode
13504CFG.EXE Program Requirements
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13504CFG View Menu
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13504CFG.EXE
Program Requirements
Installation
Usage
Script Mode
Interactive Mode
13504CFG Menu Bar
Making 13504CFG Menu Selections
Files Menu
View Menu
13504CFG Current Configuration
Device Menu
Panel
Edit Panel Setup
CRT
Edit CRT Setup
Advanced Memory
Edit Advanced Memory Setup
Power Management
Edit Power Setup
Lookup Table LUT
Edit LUT Setup
Setup
Help Menu
Comments
Sample Program Messages
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13504SHOW Demonstration Program
Document Number X19A-B-002-05
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13504SHOW
S1D13504 Supported Evaluation Platforms
Error Too many devices registered
Program Messages
13504SPLT Display Utility
Document Number X19A-B-003-05
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13504SPLT
13504SPLT Example
Comments
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13504VIRT Display Utility
Document Number X19A-B-004-05
S1D13504 13504VIRT Display Utility X19A-B-004-05
13504VIRT
13504VIRT Example
Comments
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13504PLAY Diagnostic Utility
Document Number X19A-B-005-05
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13504PLAY
Reads/writes the registers
13504PLAY Example
Scripting
Comments
13504BMP Demonstration Program
Document Number X19A-B-006-04
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13504BMP
Program Messages
13504PWR Software Suspend Power Sequencing Utility
Document Number X19A-B-007-04
X19A-B-007-04 Issue Date 01/02/01
13504PWR
Selects software suspend
Error Unknown command line argument
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13504DCFG Configuration Program
Document Number X19A-B-008-02
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Table of Contents
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List of Figures
Clocks Tab Panel Tab
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13504DCFG
Installation
Usage
13504DCFG Configuration Tabs
General Tab
General Tab
Memory Tab
Memory Tab
Clocks Tab
Clocks Tab
Clocks Tab
Clki
LCD Mclkpclk
CRT Mclkpclk
Panel Tab
Panel Tab
Panel Tab
STN/TFT
HRTC/FPLINE
VRTC/FPFRAME
CRT Tab
CRT Tab
Defaults Tab
Defaults Tab
Select the default display device. Three display modes LCD
Initializes the registers based on the default mode
Registers Tab
Registers Tab
Miscellaneous Flags Tab
Miscellaneous Flags Tab
Saving to a File
Resolution Frame Rate Hz Pclk MHz Supported Dram Types
Comments
Windows CE Display Drivers
Document Number X19A-E-001-04
X19A-E-001-04
DIP Switch
Program Requirements
Example Driver Builds
Windows Version
With this line
Build For Cepc
If CEPCDDIVGA2BPP
Epson Research and Development
Installation for Hitachi D9000 and Etma ODO
Example Installation
Installation for Cepc Environment
Comments
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Wind River WindML v2.0 Display Drivers
Document Number X19A-E-002-03
X19A-E-002-03 Issue Date 01/04/06
Wind River WindML v2.0 Display Drivers
Building a WindML v2.0 Display Driver
Make CPU=PENTIUM ugl
Epson Research and Development
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Wind River UGL v1.2 Display Drivers
Document Number X19A-E-003-02
X19A-E-003-02
Wind River UGL v1.2 Display Drivers
Building a UGL v1.2 Display Driver
Epson Research and Development
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Document Number X19A-G-004-06
S1D13504 X19A-G-004-06 Issue Date 01/02/02
Installation and Configuration
Parts List Schematic Diagrams
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S1D13504B00C Schematic Diagram 1 of 6
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Features
Installation and Configuration
Configuration DIP Switch Settings
Jumper Settings
Host Bus Selection
LCD Signal Connector J6
LCD / Ramdac Interface Pin Mapping
CPU/BUS Connector H1 Pinout
CPU / BUS Interface Connector Pinouts
Connector Comments Pin No
CPU/BUS Connector H2 Pinout
Host Bus Interface Pin Mapping
DB150 D150 D3116 WE1#
Technical Description
ISA Bus Support
Non-ISA Bus Support
Dram Support
Decode Logic
Clock Input Support
Monochrome LCD Panel Support
Color Passive LCD Panel Support
Color TFT LCD Panel Support
External Cmos Ramdac Support
Power Save Modes
Core VDD Power Supply
IO VDD Power Supply
Adjustable LCD Panel Negative Power Supply
Schematic Notes
15 CPU/Bus Interface Header Strips
Parts List
Item # Qty/board Designation Part Value Description
TIBPAL22V10-15BCNT
Texas Instrument PAL 24 pin DIP package/socketed
Schematic
Diagrams
S1D13504B00C Schematic Diagram 2
Rev.1.0
S1D13504B00C Schematic Diagram 4
Diagram 5
S1D13504B00C Schematic Diagram 6
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S5U13504-D9000
Document Number X19A-G-003-05
S5U13504-D9000 X19A-G-003-05 Issue Date 01/02/02
Introduction Features
D9000 Specifics
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S5U13504-D9000 Perspective View
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Reference
S1D13504 Color Graphics LCD Controller
Display Buffer
LCD Display Support
LCD Connector Pinout
LCD Interface Pin Mapping
Adjustable LCD Bias Power Supply
CRT Support
Interface Signals
Connector Pinout for Channel A6 and A7
Interface Signals
D9000 Specifics
GND
Connector Pinout for Channel A7
DC12V
Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ
Channel A6 Pin # Fpga Signal S1D13504 Signal SmXY
Connectors Pinout for Channel A6
BS# GND
Channel A6 Pin # Fpga Signal S1D13504 Signal SmZ
Board Dimensions
Bus Interface Timing
Memory Address CS#, M/R# Decode
Makefpga file
Parts List
Item # Qty Reference Part Description
Schematic
S5U13504-D9000 Schematic Diagram 2
S5U13504-D9000 Schematic Diagram 3
D9000
PCB Layout Component Placement
Component Placement
Perspective View
S5U13504-D9000 Perspective View
Power Consumption
Document Number X19A-G-006-04
S1D13504 Power Consumption X19A-G-006-04
S1D13504 Power Consumption
Summary
S1D13504 Total Power Consumption
Conditions
Interfacing to the Philips Mips PR31500/PR31700 Processor
Document Number X19A-G-005-08
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Direct Connection to the Philips PR31500/PR31700
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S1D13504 to PR31500/PR31700 Connection using One IT8368E
List of Tables
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Introduction
Interfacing to the PR31500/PR31700
WAIT# RESET#
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Pin Mapping
S1D13504 Generic MPU Pin Names
Generic MPU Host Bus Interface Signals
Direct Connection to the Philips PR31500/PR31700
Hardware Description
Memory Mapping and Aliasing
MD1 MD2
S1D13504 Configuration
MD3 MD4
System Design Using the IT8368E PC Card Buffer
Hardware Description-Using One IT8368E
Chip Select
Logic
Vancouver Design Center
Hardware Description-Using Two IT8368E’s
PR31500/PR31700 S1D13504
IT8368E Configuration
TX3912 Address Size Function CARDnIOEN=0 CARDnIOEN=1
IT8368E Uses PC Card Slot # Philips Address Size Function
S1D13504 Configuration using the IT8368E
Software
Documents
References
Document Sources
Technical Support
Epson LCD/CRT Controllers S1D13504
Philips Mips PR31500/PR31700 Processor
ITE IT8368E
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Interfacing to the NEC VR4102 Microprocessor
Document Number X19A-G-007-07
X19A-G-007-07 Issue Date 01/02/02
Introduction Interfacing to the NEC VR4102
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NEC VR4102 Read/Write Cycles
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Introduction
NEC VR4102 System Bus
Interfacing to the NEC VR4102
Overview
LCD Memory Access Cycles
Lcdrdy
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Read/Write
VR4102 to S1D13504 Interface
Decode Logic
S1D13504 Hardware Configuration
Generic bus interface e.g. MPC821, ISA bus interface
NEC VR4102 Configuration
NEC Signals Cycle S1D13504 Signals
WR#
Write
Software
References
NEC Electronics Inc. VR4102
Japan North America Taiwan, R.O.C
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Interfacing to the Motorola MCF5307 Coldfire Microprocessor
X19A-G-011-07 Issue Date 01/02/02
S1D13504 Bus Interface
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List of Tables
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Introduction
MCF5307 System Bus
Interfacing to the MCF5307
Normal Non-Burst Bus Transactions
MCF5307 Memory Read Cycle
Chip-Select Module
Burst Cycles
S1D13504 Bus Interface
Generic MPU Host Bus Interface Signals
MCF5307 To S1D13504 Interface
Hardware Connections
S1D13504 Configuration Settings
MCF5307 Chip Select Configuration
Memory/Register Mapping
Software
Motorola Inc. Motorola Literature Distribution Center, 800
Motorola MCF5307 Processor
S1D13504 Color Graphics LCD / CRT Controller
X19A-G-013-02 Issue Date 01/02/02
Introduction Interfacing to the MC68328
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Generic MPU Host Bus Interface Pin Mapping
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Introduction
Interfacing to the MC68328
68328 System Bus
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Busclk RESET#
MC68328 To S1D13504 Interface
CSB3 Dtack UWE LWE CLK0
MD6
MD7
MC68328 Chip Select Configuration
Option Memory Selection
Software
References
Motorola MC68328 Processor
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Interfacing to the Motorola MPC821 Microprocessor
X19A-G-010-05 Issue Date 01/02/02
Introduction Interfacing to the MPC821
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List of Tables
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Introduction
MPC8xx System Bus
Interfacing to the MPC821
MPC821 Bus Overview
Power PC Memory Read Cycle
Power PC Memory Write Cycle
Memory Controller Module
General-Purpose Chip Select Module Gpcm
User-Programmable Machine UPM
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
MPC821 to S1D13504 Interface
Typical Implementation of MPC821 to S1D13504 Interface
AB9
AB8
AB7
AB6
Sreset
Sysclk
CS4
WE0
S1D13504 Hardware Configuration
MPC821 Chip Select Configuration
Register/Memory Mapping
Test Software
Source Code
Epson Research and Development
Software
References
Motorola MPC821 Processor
Interfacing to the PC Card Bus
Document Number X19A-G-009-05
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Introduction Interfacing to the PC Card Bus
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PC Card Read Cycle
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Introduction
Memory Access Cycles
Interfacing to the PC Card Bus
PC Card System Bus
PC Card Overview
PC Card Read Cycle
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
PC Card to S1D13504 Interface
Typical Implementation of PC Card to S1D13504 Interface
SH-3
Generic MPU
PAL Equations
Equations
Software
PCMCIA/JEIDA, PC Card Standard -- March
PC Card Standard
Pcmcia
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Interfacing to the Toshiba Mips TX3912 Processor
Document Number X19A-G-012-04
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Direct Connection to the Toshiba TX3912
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S1D13504 to TX3912 Connection using One IT8368E
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Introduction
Interfacing to the TX3912
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Direct Connection to the Toshiba TX3912
Memory Mapping and Aliasing
S1D13504 Hardware Configuration
System Design Using the IT8368E PC Card Buffer
S1D13504 to TX3912 Connection using One IT8368E
Hardware Description-Using Two IT8368E’s
S1D13504 to TX3912 Connection using Two IT8368E
IT8368E Configuration
64Mb
64Mb Card 2 Attribute
64Mb Card 1 Memory
64Mb Card 2 Memory
S1D13504 Configuration
Software
References
Toshiba Mips TX3912 Processor ITE IT8368E
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RESET
/REFRESH
BUSCLK
BALE