Epson S1D13504 CRT Considerations, Introduction, CRT Only, Register Name Little-Endian Big-Endian

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6 CRT Considerations

6.1 Introduction

The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Frame Rate Calculation (Chapter 11)” in S1D13504 Hardware Functional Specification. The following sections describe CRT considerations.

6.1.1 CRT Only

For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel. The monitor configuration registers then need to be set to follow the VESA timing standard.

Note

If only the CRT is used, it is also useful to disable the LCD power (set REG[1Ah] bit 4 = 1). This will reduce power consumption.

To program the external RAMDAC, set the CRT Enable bit in the Display Mode Register (REG[0Dh]) to 1. Once the CRT is enabled, the GPIO registers will be automatically set to access the external RAMDAC. Next, program the RAMDAC Write Mode Address register and the RAMDAC Palette Data register as desired (refer to sample code in 9.1.2 for details).

When programming the RAMDAC control registers, connect the RAMDAC to the low-byte of the CPU data bus for Little-Endian architecture and the high-byte for Big-Endian architecture. The RAMDAC registers are mapped as follows:

Table 6-1: RAMDAC Register Mapping for Little/Big-Endian

Register Name	Little-Endian	Big-Endian
RAMDAC Pixel Read Mask	REG[28h]	REG[29h]
RAMDAC Read Mode Address	REG[2Ah]	REG[2Bh]
RAMDAC Write Mode Address	REG[2Ch]	REG[2Dh]
RAMDAC Palette Data	REG[2Eh]	Reg[2Fh]

Note

When accessing the External RAMDAC Control registers with either of the Little-Endian or Big-Endian architectures described above, accessing the adjacent unused registers is prohibited.

Table 6-2 shows some example register data for setting up CRT only mode for certain combinations of resolutions, frame rates and pixel clocks. All the examples in this chapter are assumed to be for a Little-Endian system, 8 bpp color depth and 2M bytes of 60ns EDO-DRAM.

Programming Notes and Examples	S1D13504
Issue Date: 01/02/01	X19A-G-002-07