Power Save Mode Function Summary | Epson S1D13504 manual

Epson Research and Development	Page 129
Vancouver Design Center

13.3 Power Save Mode Function Summary

Table 13-1: Power Save Mode Function Summary

		Power Save Mode (PSM)
Function
Function	Normal		Software	Hardware
	(Active)		Suspend	Suspend

Display Active?	Yes		No	No

Register Access Possible?	Yes		Yes (1)	No

Memory Access Possible?	Yes		No	No

Host Bus Interface Running?	Yes		Yes	No

Memory Interface Running?	Yes		No (2)	No (2)

Note

(1)except for RAMDAC registers.

(2)Yes if CBR suspend mode refresh is selected.

13.4Pin States in Power Save Modes

Table 13-2: Pin States in Power Save Modes

			Pin State
Pins
Pins		Normal	Software	Hardware
		(Active)	Suspend	Suspend

LCD outputs		Active	Forced Low (1)	Forced Low (1)

LCDPWR		On	Off	Off

DRAM outputs		Active	Refresh Only (2)	Refresh Only (2)

CRT / DAC outputs		Active	Disabled (3)	Disabled (3)

Host Interface outputs		Active	Active (4)	Disabled

Note
1.	FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6
	and REG[07h] bit 6 respectively.
2.	Selectable: may be CBR refresh, self-refresh or no refresh at all.
3.	DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled.
4.	Active for non-DAC register access only.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18

Image 135

Epson S1D13504 manual Power Save Mode Function Summary, Pin States in Power Save Modes, Power Save Mode PSM

Contents

Document Number X19A-Q-002-14 Technical Manual This page Left Blank Customer Support Information This page Left Blank CPU Interface Power Down ModesGeneral Purpose IO pins Memory Interface Ramdac CPU Document Number X19A-A-002-18 Hardware Functional Specification X19A-A-002-18 Issue Date 01/01/30 Table of Contents Registers Clocking 119 Display Configuration 116Power Save Modes 128 Display Buffer This page Left Blank List of Tables Vancouver Design Center List of Figures Vancouver Design Center Introduction ScopeOverview Description Display Support FeaturesMemory Interface CPU Interface Package and Pin Display ModesClock Source Miscellaneous LCD Typical System Implementation Diagrams Management MC68000 Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM Memory Controller Functional Block DiagramBlock Description Functional Block Descriptions Host Interface Power Save Look-Up TableLCD Interface Pinout Diagram for S1D13504F00A Pin OutPackage type 128 pin surface mount QFP15 Package type 128 pin surface mount TQFP15 Pinout Diagram for S1D13504F01A Package type 144 pin surface mount QFP20 Pinout Diagram for S1D13504F02A TS2 Pin DescriptionKey AB0 RD/WR# CS#Busclk BS# WAIT# TS2 RESET# RAS# CO1 LCAS# CO1UCAS# CO1 WE# CO1 MA9 TS1 LCD Interface Pin Descriptions Clock Input CRT and External Ramdac Interface BLANK# CN3 CRT and Ramdac Interface Pin DescriptionsHrtc Vrtc Pin # Pin Name Type Driver Description F00A F02A F01A Power Supply Summary of Configuration Options Asym 1Mx16 Multiple Function Pin MappingS1D13504 SH-3 MC68K Bus Generic MPU Pin Names Asym 256Kx16 11 LCD, CRT, Ramdac Interface Pin Mapping C. Characteristics Symbol Parameter Rating UnitsSymbol Parameter Condition Min Typ Max Units Bidirectional Pin Capacitance Low Level Output VoltageOutput Leakage Current Output Pin Capacitance CPU Interface Timing 1 SH-3 Interface Timing RD/WR# BS#WAIT# Symbol Parameter Min Max Units 2 MC68K Bus 1 Interface Timing e.g. MC68000 AS# UDS# LDS#T13 T14 T15 D150read D150 valid to DTACK# falling edge read cycle AS# high setup to CLKAS# high to DTACK# high impedance D150 hold from falling edge of DTACK# write cycle T13 T14 T15 3 MC68K Bus 2 Interface Timing e.g. MC68030A200 SIZ10 M/R# AS# DS# D3116 valid to DSACK1# falling edge read cycle D3116 hold from falling edge of DSACK1# write cycle RD0#,RD1# WE0#,WE1# Hi-Z Generic MPU Interface Synchronous TimingBclk A200 Low write cycle D150 hold from WE0#, WE1# high write cycle Generic MPU Interface Asynchronous Timing A200 ValidHi-Z Valid T10 D150read T82 Clock Input Requirements Symbol Parameter Min Typ Max Units RAS# CAS# Memory Interface Timing EDO-DRAM Read Timing EDO Dram Read Timing RAS# CAS# WE# EDO-DRAM Write Timing 55 t1 + CAS# precharge time 45 t1 T14 Write Data setup time 45 t1 T15 Write Data hold time EDO-DRAM Read-Write Timing EDO-DRAM Read-Write Timing EDO Dram Read-Write Timing 10 EDO-DRAM CAS Before RAS Refresh Timing EDO-DRAM CAS Before RAS Refresh Timing 11 EDO-DRAM Self-Refresh Timing EDO-DRAM Self-Refresh Timing 12 FPM-DRAM Read Timing FPM-DRAM Read Timing 12 FPM Dram Read Timing 13 FPM-DRAM Write Timing FPM-DRAM Write Timing T14 Write Data setup time 45 t1 T15 Write Data hold time 14 FPM-DRAM Read-Write Timing FPM-DRAM Read-Write Timing 45 t1 S1D13504 RAS# precharge time REG22h bits 32 = 01 or 45 t1 FPM-DRAM CAS# Before RAS# Refresh Timing 16 FPM-DRAM CBR Self-Refresh Timing FPM-DRAM Self-Refresh Timing Fpframe active Display Interface Power-On/Reset Timing Mclk Suspend Timing HDP = Single Monochrome 4-Bit Panel TimingVDP = Vndp = Data Timing Sync Timing HDP Single Monochrome 8-Bit Panel TimingVDP Vndp = REG05h bits 40 + 1*8 14 Ts UD30, LD30 setup to Fpshift falling edgeUD30, LD30 hold to Fpshift falling edge = REG05h bits 40 + 1*8 23 Ts 23 Single Color 4-Bit Panel Timing Single Color 4-Bit Panel Timing = REG04h bits 60+1*8 1 Ts = REG05h bits 40 + 1*8 26 Ts= REG05h bits 40 + 1*8 17 Ts 25 Single Color 8-Bit Panel Timing Format Single Color 8-Bit Panel Timing Format FPSHIFT2, Fpshift pulse width high UD30, LD30 setup to FPSHIFT2 rising, Fpshift falling edgeFpline pulse width Fpline period FPSHIFT2 falling edge to Fpline rising edge 27 Single Color 8-Bit Panel Timing Format T1min = t3min 9Ts VDP Vndp LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP Hndp Single Color 16-Bit Panel Timing UD70, LD70 hold to Fpshift falling edge UD70, LD70 setup to Fpshift falling edge Fpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Monochrome 8-Bit Panel Timing = REG05h bits 40 + 1*8 8 Ts 33 Dual Color 8-Bit Panel Timing Dual Color 8-Bit Panel Timing = REG05h bits 40 + 1*8 9 Ts 35 Dual Color 16-Bit Panel Timing Dual Color 16-Bit Panel Timing UD70 LD70 = Vertical Display Period = REG09h bits 10, REG08h bits 70 + 12 16-Bit TFT Panel Timing 38 TFT A.C. Timing = REG04h bits 60+1*8 + REG05h bits 40+1*8 Ts = REG07h bits 30+1*8 Ts= REG0Ch bits 20+1 lines 39 CRT Timing CRT Timing 40 CRT A.C. Timing Dacclk period DACWR# pulse width low External Ramdac Read / Write TimingRead Write Revision Code Register RegistersRegister Mapping Register Descriptions Memory Configuration Registers Memory Configuration RegisterTime/256 Cycles REG03h MOD Rate Bit Panel/Monitor Configuration RegistersPanel Type Register MOD Rate Register Horizontal Display Width Register Horizontal Non-Display Period RegisterHRTC/FPLINE Start Position Register HRTC/FPLINE Pulse Width Register Vertical Display Height RegisterHrtc Fpline Vertical Non-Display Period Register VRTC/FPFRAME Start Position RegisterVrtc Fpframe Vrtc Polarity VRTC/FPFRAME Pulse Width RegisterREG0Ch Fpframe Vrtc Even Scan Only Display Configuration RegistersDisplay Mode Register Simultaneous Display Option Select Bits Number of Bits-Per-Pixel Selection Screen 1 Display Start Address Register Screen 1 Line Compare Register Screen 2 Display Start Address Register 0 RW Screen 2 Display Start Address RegisterMemory Address Offset Register Number of Bits-Per-Pixel Screen 2 Pixel Panning Bits Used Clock Configuration RegisterClock Configuration Register Pixel Panning Register Miscellaneous Registers Power Save Configuration RegistersPower Save Configuration Register Miscellaneous Disable Register MD9 MD8 MD Configuration Readback RegisterGpio Configuration Register REG1Dh MD15 MD14 MD13 MD12 MD11 MD10 Vancouver Design Center REG1Fh GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config Gpio Status / Control Register GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin Control IO Status Gpio Status / Control RegisterREG21h GPO Minimum Random Cycle Width t RC Performance Enhancement RegisterREG22h EDO Read RC Timing RAS# to REG22h Bits RAS# Precharge Width t RP RAS# to CAS# Delay tRCDOptimal Dram Timing REG22h Bit RGB Index Bits Look-Up Table Access Pointer Sequence Look-Up Table RegistersLook-Up Table Address Register REG27h Red Bank Blue Bank Green Bank Select Bit Look-Up Table Data RegisterLook-Up Table Bank Select Register REG26h LUT Data Bit Ramdac Pixel Read Mask Register Ramdac Read Mode Address RegisterRamdac Write Mode Address Register External Ramdac Control Registers REG2Eh or REG2Fh Ramdac Palette Data Register 512K byte Memory AB200 Display Buffer Half Frame Buffer Image Buffer Display Mode Data Format Display Configuration 15/16 Bit-Per-Pixel Format Memory Organization Image Manipulation DisplayImage Buffer Maximum Pclk Allowed Bpp 16 bpp ClockingMaximum Mclk Pclk Ratios Display type MHz Frame Rate Calculation= Pclk Speed Grade Bpp Clock Hndpt s Panel FPM-DRAM Gray Shade Display Modes Bit-Per-Pixel ModeDisplay Mode Bit Wide Look-Up Table Look-Up Table Architecture Bit-Per-Pixel Mode Color Display Modes Bit-Per-Pixel Color Mode Bank Selected Bank Entry Bit Red data output Logic Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110 Color Data Format Red Look-Up Table Power Save Modes Hardware SuspendSoftware Suspend Pin State Pins Normal Software Hardware Active Suspend Power Save Mode Function SummaryPin States in Power Save Modes Power Save Mode PSM Mechanical Data 14.1 QFP15-128 S1D13504F00AQFP15 128 pin Unit mm TQFP15-128 S1D13504F01A TQFP15 128 pin Unit mm±0.2 QFP20-144 S1D13504F02A QFP20 144 pin Unit mm125 Document Number X19A-G-002-07 Programming Notes and Examples This page Left Blank LCD Power Sequencing and Power Save Modes Introduction Programming the S1D13504 RegistersAdvanced Techniques Appendix a Supported Panel Values CRT ConsiderationsIdentifying the S1D13504 Hardware Abstraction Layer HAL Sample Code Initializing the S1D13504 Registers This page Left Blank Introduction Programming the S1D13504 Registers 2 REG22 bits 7-2 Performance Enhancement Register3 REG02 bit 1 Dual/Single Panel Type 4 REG1B bit 0 Half Frame Buffer Disable 5 REG23 Display FifoRegister Initialization Initialization Sequence Initialization Example Initializing the S1D13504 RegistersOperation Description Disabling the Half Frame Buffer Sequence Re-Programming Registers Display Buffer Location BitPixel Bit Bit Red Bit Green Bit Blue Bit Memory Organization for Eight Bit-per-pixel 256 Colors Memory Organization for 15 Bit-per-pixel 32768 Colors Memory Organization for 16 Bit-per-pixel 65536 ColorsBit Reserved Red Bit Green Bit Blue Bit REG27h Look-Up Table Bank Register Read/Write Look-Up Table LUTREG24h Look-Up Table Address Register Read/Write REG26h Look-Up Table Data Register Read/Write Bank Select Bits Look-Up Table Configurations Look-Up Table OrganizationBank Address Red Green Blue Recommended LUT Values for 1 bpp Color ModeRecommended LUT Values for 2 bpp Color Mode Color Modes 11 Recommended LUT Values For 8 bpp Color Mode Pixel Value Color 12 Examples of 256 Pixel Colors Using Linear LUTGray Shade Modes 13 Recommended LUT Values for 1 bpp Gray Shades 14 Recommended LUT Values for 2 bpp Gray Shades 15 Recommended LUT Values for 8 bpp Gray ShadeLUT Address Green LUT Data Bpp Gray Shade Virtual Display Advanced Technique s REG17h Memory Address Offset Register RegistersExamples REG16h Memory Address Offset Register Panning and Scrolling Active Pixel Pan Bits Number of Pixels Panned Using Start Address Example 4 Panning Right and Left REG0F Screen 1 Line Compare Register Split ScreenREG0E Screen 1 Line Compare Register Line Compare Bit REG13h Screen 2 Display Start Address Register REG14h Screen 2 Display Start Address RegisterREG15h Screen 2 Display Start Address Register Display Mode Register LCD Power Sequencing and Power Save ModesIntroduction to LCD Power Sequencing Introduction to Power Save Modes Suspend Sequencing Suspend Enable SequenceShortening the 128 Frame delay using Software Suspend Shortening the 128 Frame Delay using Hardware SUSPEND# LCD Enable / Disable using Manual Control Suspend Disable SequenceLCD Enable/Disable Sequencing Reg0D bit LCD Enable / Disable using Power Save Modes Ramdac Register Mapping for Little/Big-Endian CRT ConsiderationsIntroduction CRT Only Related Register Data for CRT Only Simultaneous Display Address Address Register 640X480@75Hz 640X480@60Hz Related register data for Simultaneous Display Identifying the S1D13504 Hardware Abstraction Layer HAL API for 13504HALInitialization Int seDeRegisterDeviceint device Int seInitHalvoid Int seGetIdint device, Byte *pId Int seSetInitint device Int seValidRegisteredDeviceint deviceInt seValidStdDeviceint device Int seGetLinearDispAddrint device, Dword *pDispLogicalAddr Int seGetBitsPerPixelint device, Byte *pBitsPerPixelInt seGetBytesPerScanlineint device, int *pBytes Int seGetLastUsableByteint device, Dword *pLastByte Int seGetScreenSizeint device, int *width, int *height Int seReadDisplayByteint device, Dword offset, Byte *pByteInt seReadDisplayWordint device, Dword offset, Word *pWord Int seSplitInitint device, Dword Scrn1Addr, Dword Scrn2Addr Int seSetBitsPerPixelint device, Byte BitsPerPixel Int seVirtMoveint device, Byte WhichScreen, int x, int y Int seVirtInitint device, int xVirt, long *yVirt Vancouver Design Center Color Manipulation Int seGetDacint device, Byte *pDac Int seGetDacEntryint device, Byte index, Byte *pEntryInt seGetLutint device, Byte *pLut Int seGetLutEntryint device, Byte index, Byte *pEntry Int seSetDacint device, Byte *pDacInt seSetDacEntryint device, Byte index, Byte *pEntry Int seSetLutEntryint device, Byte index, Byte *pEntry Int seSetLutint device, Byte *pLut Int seDrawTextint device, char *fmt Int seGetcharvoid Int sePutcharint chInt sePutcint device, int ch Miscellaneous Int seDelayint device, Dword Seconds Int seSetPixelint device, int x, int y, Dword colorInt seSetRegint device, int index, Byte val Word seRotateByteRightBYTE val, Byte bits Word seRotateByteLeftBYTE val, Byte bits Sample Code Sample code using 13504HAL API Sample code without using 13504HAL API Vancouver Design Center Pclk To arrive at the frame rate closest to the desired Words Fifo Passive Dual Panel Appendix a Supported Panel ValuesSupported Panel Values Passive Single Panel TFT 16-Bit Register Single TFT Panel 01/02/02 Number of Bits/Pixel Document Number X19A-B-001-04 13504CFG.EXE Configuration Program Vancouver Design Center X19A-B-001-04 13504CFG.EXE Program Requirements Script Mode Interactive Mode This page Left Blank 13504CFG View Menu This page Left Blank 13504CFG.EXE Installation Program RequirementsUsage Script Mode 13504CFG Menu Bar Interactive Mode Making 13504CFG Menu Selections Files Menu View Menu 13504CFG Current Configuration Device Menu Panel Edit Panel Setup CRT Edit CRT Setup Advanced Memory Edit Advanced Memory Setup Power Management Edit Power Setup Lookup Table LUT Edit LUT Setup Setup Help Menu Sample Program Messages Comments This page Left Blank Document Number X19A-B-002-05 13504SHOW Demonstration Program This page Left Blank S1D13504 Supported Evaluation Platforms 13504SHOW Program Messages Error Too many devices registered Document Number X19A-B-003-05 13504SPLT Display Utility This page Left Blank 13504SPLT 13504SPLT Example Comments This page Left Blank Document Number X19A-B-004-05 13504VIRT Display Utility S1D13504 13504VIRT Display Utility X19A-B-004-05 13504VIRT 13504VIRT Example Comments This page Left Blank Document Number X19A-B-005-05 13504PLAY Diagnostic Utility This page Left Blank 13504PLAY Reads/writes the registers Scripting 13504PLAY Example Comments Document Number X19A-B-006-04 13504BMP Demonstration Program This page Left Blank 13504BMP Program Messages Document Number X19A-B-007-04 13504PWR Software Suspend Power Sequencing Utility X19A-B-007-04 Issue Date 01/02/01 13504PWR Selects software suspend Error Unknown command line argument This page Left Blank Document Number X19A-B-008-02 13504DCFG Configuration Program This page Left Blank Table of Contents This page Left Blank Clocks Tab Panel Tab List of Figures This page Left Blank Installation 13504DCFGUsage 13504DCFG Configuration Tabs General Tab General Tab Memory Tab Memory Tab Clocks Tab Clocks Tab CRT Mclkpclk Clocks TabClki LCD Mclkpclk Panel Tab Panel Tab VRTC/FPFRAME Panel TabSTN/TFT HRTC/FPLINE CRT Tab CRT Tab Initializes the registers based on the default mode Defaults TabDefaults Tab Select the default display device. Three display modes LCD Registers Tab Registers Tab Miscellaneous Flags Tab Miscellaneous Flags Tab Saving to a File Comments Resolution Frame Rate Hz Pclk MHz Supported Dram Types Document Number X19A-E-001-04 Windows CE Display Drivers X19A-E-001-04 Windows Version DIP SwitchProgram Requirements Example Driver Builds With this line Build For Cepc If CEPCDDIVGA2BPP Epson Research and Development Example Installation Installation for Hitachi D9000 and Etma ODOInstallation for Cepc Environment Comments This page Left Blank Document Number X19A-E-002-03 Wind River WindML v2.0 Display Drivers X19A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers Make CPU=PENTIUM ugl Building a WindML v2.0 Display Driver Epson Research and Development This page Left Blank Document Number X19A-E-003-02 Wind River UGL v1.2 Display Drivers X19A-E-003-02 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Document Number X19A-G-004-06 S1D13504 X19A-G-004-06 Issue Date 01/02/02 Parts List Schematic Diagrams Installation and Configuration This page Left Blank S1D13504B00C Schematic Diagram 1 of 6 This page Left Blank Features Host Bus Selection Installation and ConfigurationConfiguration DIP Switch Settings Jumper Settings LCD / Ramdac Interface Pin Mapping LCD Signal Connector J6 CPU / BUS Interface Connector Pinouts CPU/BUS Connector H1 PinoutConnector Comments Pin No CPU/BUS Connector H2 Pinout DB150 D150 D3116 WE1# Host Bus Interface Pin Mapping ISA Bus Support Technical Description Clock Input Support Non-ISA Bus SupportDram Support Decode Logic External Cmos Ramdac Support Monochrome LCD Panel SupportColor Passive LCD Panel Support Color TFT LCD Panel Support Adjustable LCD Panel Negative Power Supply Power Save ModesCore VDD Power Supply IO VDD Power Supply 15 CPU/Bus Interface Header Strips Schematic Notes Item # Qty/board Designation Part Value Description Parts List Texas Instrument PAL 24 pin DIP package/socketed TIBPAL22V10-15BCNT Diagrams Schematic S1D13504B00C Schematic Diagram 2 Rev.1.0 S1D13504B00C Schematic Diagram 4 Diagram 5 S1D13504B00C Schematic Diagram 6 This page Left Blank Document Number X19A-G-003-05 S5U13504-D9000 S5U13504-D9000 X19A-G-003-05 Issue Date 01/02/02 D9000 Specifics Introduction Features This page Left Blank S5U13504-D9000 Perspective View This page Left Blank Reference Display Buffer S1D13504 Color Graphics LCD Controller LCD Display Support LCD Interface Pin Mapping LCD Connector Pinout CRT Support Adjustable LCD Bias Power Supply D9000 Specifics Interface SignalsConnector Pinout for Channel A6 and A7 Interface Signals Connector Pinout for Channel A7 GNDDC12V Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ Connectors Pinout for Channel A6 Channel A6 Pin # Fpga Signal S1D13504 Signal SmXYBS# GND Channel A6 Pin # Fpga Signal S1D13504 Signal SmZ Makefpga file Board DimensionsBus Interface Timing Memory Address CS#, M/R# Decode Item # Qty Reference Part Description Parts List Schematic S5U13504-D9000 Schematic Diagram 2 S5U13504-D9000 Schematic Diagram 3 D9000 Component Placement PCB Layout Component Placement S5U13504-D9000 Perspective View Perspective View Document Number X19A-G-006-04 Power Consumption S1D13504 Power Consumption X19A-G-006-04 S1D13504 Power Consumption S1D13504 Total Power Consumption SummaryConditions Document Number X19A-G-005-08 Interfacing to the Philips Mips PR31500/PR31700 Processor This page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank List of Tables S1D13504 to PR31500/PR31700 Connection using One IT8368E This page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13504 Generic MPU Pin Names WAIT# RESET#S1D13504 Host Bus Interface Generic MPU Host Bus Interface Pin Mapping Generic MPU Host Bus Interface Signals Hardware Description Direct Connection to the Philips PR31500/PR31700 Memory Mapping and Aliasing S1D13504 Configuration MD1 MD2MD3 MD4 Hardware Description-Using One IT8368E System Design Using the IT8368E PC Card Buffer Logic Chip Select Vancouver Design Center PR31500/PR31700 S1D13504 Hardware Description-Using Two IT8368E’s IT8368E Configuration IT8368E Uses PC Card Slot # Philips Address Size Function TX3912 Address Size Function CARDnIOEN=0 CARDnIOEN=1 S1D13504 Configuration using the IT8368E Software References DocumentsDocument Sources ITE IT8368E Technical SupportEpson LCD/CRT Controllers S1D13504 Philips Mips PR31500/PR31700 Processor This page Left Blank Document Number X19A-G-007-07 Interfacing to the NEC VR4102 Microprocessor X19A-G-007-07 Issue Date 01/02/02 Introduction Interfacing to the NEC VR4102 This page Left Blank NEC VR4102 Read/Write Cycles This page Left Blank Introduction Interfacing to the NEC VR4102 NEC VR4102 System BusOverview Lcdrdy LCD Memory Access Cycles S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals VR4102 to S1D13504 Interface Read/WriteDecode Logic Generic bus interface e.g. MPC821, ISA bus interface S1D13504 Hardware Configuration Write NEC VR4102 ConfigurationNEC Signals Cycle S1D13504 Signals WR# Software References Japan North America Taiwan, R.O.C NEC Electronics Inc. VR4102 This page Left Blank Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A-G-011-07 Issue Date 01/02/02 S1D13504 Bus Interface This page Left Blank List of Tables This page Left Blank Introduction Interfacing to the MCF5307 MCF5307 System BusNormal Non-Burst Bus Transactions MCF5307 Memory Read Cycle Burst Cycles Chip-Select Module S1D13504 Bus Interface Generic MPU Host Bus Interface Signals Hardware Connections MCF5307 To S1D13504 Interface S1D13504 Configuration Settings Memory/Register Mapping MCF5307 Chip Select Configuration Software Motorola Inc. Motorola Literature Distribution Center, 800 Motorola MCF5307 Processor S1D13504 Color Graphics LCD / CRT Controller X19A-G-013-02 Issue Date 01/02/02 Introduction Interfacing to the MC68328 This page Left Blank Generic MPU Host Bus Interface Pin Mapping This page Left Blank Introduction 68328 System Bus Interfacing to the MC68328 S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals MC68328 To S1D13504 Interface Busclk RESET# CSB3 Dtack UWE LWE CLK0 MD7 MD6 Option Memory Selection MC68328 Chip Select Configuration Software References Motorola MC68328 Processor This page Left Blank Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-05 Issue Date 01/02/02 Introduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction Interfacing to the MPC821 MPC8xx System BusMPC821 Bus Overview Power PC Memory Read Cycle Power PC Memory Write Cycle General-Purpose Chip Select Module Gpcm Memory Controller Module User-Programmable Machine UPM S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of MPC821 to S1D13504 Interface MPC821 to S1D13504 Interface AB6 AB9AB8 AB7 WE0 SresetSysclk CS4 S1D13504 Hardware Configuration Register/Memory Mapping MPC821 Chip Select Configuration Source Code Test Software Epson Research and Development Software References Motorola MPC821 Processor Document Number X19A-G-009-05 Interfacing to the PC Card Bus This page Left Blank Introduction Interfacing to the PC Card Bus This page Left Blank PC Card Read Cycle This page Left Blank Introduction PC Card Overview Memory Access CyclesInterfacing to the PC Card Bus PC Card System Bus PC Card Read Cycle S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of PC Card to S1D13504 Interface PC Card to S1D13504 Interface Generic MPU SH-3 Equations PAL Equations Software PCMCIA/JEIDA, PC Card Standard -- March Pcmcia PC Card Standard This page Left Blank Document Number X19A-G-012-04 Interfacing to the Toshiba Mips TX3912 Processor This page Left Blank Direct Connection to the Toshiba TX3912 This page Left Blank S1D13504 to TX3912 Connection using One IT8368E This page Left Blank Introduction Interfacing to the TX3912 S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Direct Connection to the Toshiba TX3912 Memory Mapping and Aliasing S1D13504 Hardware Configuration System Design Using the IT8368E PC Card Buffer S1D13504 to TX3912 Connection using One IT8368E Hardware Description-Using Two IT8368E’s S1D13504 to TX3912 Connection using Two IT8368E IT8368E Configuration 64Mb Card 2 Memory 64Mb64Mb Card 2 Attribute 64Mb Card 1 Memory S1D13504 Configuration Software References Toshiba Mips TX3912 Processor ITE IT8368E This page Left Blank