Epson S1D13504 manual Power PC Memory Write Cycle

Page 10	Epson Research and Development
	Vancouver Design Center

The following figure illustrates a typical memory write cycle on the Power PC system bus.

SYSCLK

TS

TA

A[0:31]

RD/WR

TSIZ[0:1], AT[0:3]

D[0:31]	Valid
Transfer Start	Wait States	Transfer	Next Transfer
		Complete	Starts

Figure 2-2: Power PC Memory Write Cycle

If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted. For example, a peripheral device may assert TEA if a parity error is detected, or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time-out period.

For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines A30 and A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and address line A30 is ignored. For 8-bit transfers, data lines D0 through D7 are used and all address lines (A[0:31]) are used.

Note

This assumes that the Power PC core is operating in big endian mode (typically the case for embedded systems).

2.1.3Burst Cycles

Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip DMA operations. They are very similar to normal bus cycles with the following exceptions:

•Always 32-bit.

•Always attempt to transfer four 32-bit words sequentially.

•Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).

•Do not increment address bits A28 and A29 between successive transfers; the addressed device must increment these address bits internally.

If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI) simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data transfers.

S1D13504	Interfacing to the Motorola MPC821 Microprocessor
X19A-G-010-05	Issue Date: 01/02/02