Epson Research and Development

Page 9

Vancouver Design Center

 

 

 

During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle.

The figure below illustrates a typical memory read cycle on the PC Card bus.

A[25:0]

 

ADDRESS VALID

REG#

 

 

 

CE1#

 

 

CE2#

 

 

OE#

 

 

WAIT#

 

 

D[15:0]

Hi-Z

Hi-Z

 

 

DATA VALID

 

Transfer Start

Transfer Complete

Figure 2-1: PC Card Read Cycle

The figure below illustrates a typical memory write cycle on the PC Card bus.

A[25:0]

 

ADDRESS VALID

REG#

 

 

 

CE1#

 

 

CE2#

 

 

OE#

 

 

WE#

 

 

WAIT#

 

 

D[15:0]

Hi-Z

Hi-Z

 

 

DATA VALID

 

Transfer Start

Transfer Complete

Figure 2-2: PC Card Write Cycle

Interfacing to the PC Card Bus

S1D13504

Issue Date: 01/02/02

X19A-G-009-05

Page 471
Image 471
Epson S1D13504 manual PC Card Read Cycle