Epson S1D13504 manual MA9 TS1

Page 26	Epson Research and Development
	Vancouver Design Center

Table 5-2: Memory Interface Pin Descriptions (Continued)

		Pin #			Reset = 0
Pin Name	Type			Driver		Description
		F00A
			F02A		Value
		F01A
		43, 41,	46, 44,
		39, 37,	42, 40,
MA[8:0]	O	35, 34,	41, 43,	CO1	Output 0	Multiplexed memory address.
		36, 38,	45, 47,
		40	49
						This pin has multiple functions.
						• For 2M byte DRAM, this is memory address bit 9 (MA9).
						• For asymmetrical 512K byte DRAM, this is memory address
MA9	IO	45	51	C/TS1	Hi-Z /	bit 9 (MA9).
					Output 01	• For symmetrical 512K byte DRAM, this pin can be used as
						general purpose IO (GPIO3).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
						This pin has multiple functions.
						• For asymmetrical 2M byte DRAM, this is memory address bit
					Hi-Z /	10 (MA10).
MA10	IO	42	48	C/TS1		• For symmetrical 2M byte DRAM and all 512K byte DRAM,
					Output 01
						this pin can be used as general purpose IO (GPIO1).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
						This pin has multiple functions.
						• For asymmetrical 2M byte DRAM, this is memory address bit
					Hi-Z /	11 (MA11).
MA11	IO	44	50	C/TS1		• For symmetrical 2M byte DRAM and all 512K byte DRAM,
					Output 01
						this pin can be used as general purpose IO (GPIO2).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
1 When configured as IO pins.

S1D13504	Hardware Functional Specification
X19A-A-002-18	Issue Date: 01/01/30