Epson S1D13504 manual 4 REG1B bit 0 Half Frame Buffer Disable, 5 REG23 Display Fifo

Epson Research and Development	Page 9
Vancouver Design Center

2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable

This bit must not be changed while the HFB is active.

This register 'might' be disabled during normal operation for two reasons:

1.to increase bandwidth for simultaneous display.

2.to test 'all' available memory.

To disable the HFB see Section 2.3, “Disabling the Half Frame Buffer Sequence:” on page 11.

Note

The HFB is enabled after RESET (default condition). It will start to Read and Write the DRAM if the DUAL bit set + (Horizontal resolution > 0) + HFB enabled (default power-on state).

2.1.5 REG[23] Display FIFO:

This register can be asynchronously enabled/disabled.

Note

The Display FIFO starts to access DRAM after RESET.

2.2 Register Initialization

2.2.1 Initialization Sequence

To initialize the S1D13504 after POWER-ON or a HARDWARE RESET, do the following:

1.Enable the host interface (REG[1Bh] bit 7=0).

2.Disable the display FIFO (REG[23h] bit 7=1) after stopping FIFO accesses to the DRAM.

3.Set memory type (REG[01h] bit 0).

4.Set performance register (REG[22h]).

5.Set dual/single panel (REG[02h] bit 1).

6.Program all other registers as required.

7.Enable the display FIFO (REG[23h] bit 7=0).

8.Enable display.

Note

The Half Frame Buffer does not actually start to access DRAM until step 5, therefore, this initialization sequence will not cause any problems.

Programming Notes and Examples	S1D13504
Issue Date: 01/02/01	X19A-G-002-07