Epson S1D13504 manual Fpm-Dram

Epson Research and Development	Page 121
Vancouver Design Center

Table 11-3: Example Frame Rates

DRAM Type1			Color	Maximum	Minimum	Maximum Frame
				Pixel		Rate (Hz)
	Display	Resolution	Depth		Panel
(Speed Grade)			(bpp)	Clock	HNDP(Ts)	Panel4	CRT
				(MHz)
	• Single Panel.	800x6002	1/2/4/8		32	66	55
	• CRT.
			16		56	65	55
	• Dual Mono/Color Panel with Half
			1/2/4/8		32	101	78
	Frame Buffer Disabled.5	640x480
			16		56	98	78
	• Simultaneous CRT + Single Panel.
60ns	• Simultaneous CRT + Dual	640x240	1/2/4/8	33	32	203	-
	Mono/Color Panel with Half Frame		16		56	200	-
EDO-DRAM
	Buffer Disabled.5
MClk = 33MHz		480x320	1/2/4/8		32	200	-
			16		56	196	-
NRC = 4
NRP = 1.5		320x240	1/2/4/8		32	388	-
NRCD = 2
			16		56	380	-
	• Dual Color with Half Frame Buffer	800x6002,3	1/2/4/8	16.5	32	66	-
	Enabled.
			16	11	32	43	-
	• Dual Mono with Half Frame Buffer
			1/2/4/8	16.5	32	103	-
	Enabled.	640x480
			16	11	32	68	-
	• Single Panel.	800x6002	1/2/4/8		32	50	-
	• CRT.
			16		56	48	-
	• Dual Mono/Color Panel with Half
			1/2/4/8		32	77	60
	Frame Buffer Disabled.5	640x480
			16		56	75	60
	• Simultaneous CRT + Single Panel.
	• Simultaneous CRT + Dual	640x240	1/2/4/8	25	32	142	-
	Mono/Color Panel with Half Frame		16		56	136	-
60ns	Buffer Disabled.5
		480x320	1/2/4/8		32	152	-
FPM-DRAM
			16		56	145	-
MClk = 25MHz		320x240	1/2/4/8		32	294	-
NRC = 4
			16		56	280	-
NRP = 1.5
	• Dual Mono with Half Frame Buffer	800x6002	1/2/4/8/16	12.5	32	50	-
NRCD = 2
	Enabled.
		640x480	1/2/4/8/16	12.5	32	77	-
		640x400	1/2/4/8/16	12.5	32	92	-
	• Dual Color with Half Frame Buffer	800x6002,3	1/2/4/8	12.5	32	50	-
	Enabled.
			16	8.33	32	33	-
		640x480	1/2/4/8	12.5	32	77	-
			16	8.33	32	51	-

1.Must set NRC = 4MCLK. See REG[22h], “Performance Enhancement Register 0”.

2.800x600 @ 16 bpp requires 2M bytes of display buffer for all display types.

3.800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled.

4.Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down.

5.Half Frame Buffer disabled by REG[1Bh] bit 0.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18