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Epson S1D13504 manual Dual Monochrome 8-Bit Panel Timing, Fpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0

Models: S1D13504

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Epson Research and Development	Page 77
Vancouver Design Center

7.4.9 Dual Monochrome 8-Bit Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

UD[3:0], LD[3:0]

FPLINE

MOD

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

HDP			HNDP

FPSHIFT

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

1-1	1-5																1-637
1-1	1-5																1-637

1-2	1-6																1-638
1-2	1-6																1-638


1-3	1-7																										1-639
1-3	1-7																										1-639

1-4	1-8																1-640
1-4	1-8																1-640


241-1 241-5																	241-637
241-1 241-5																	241-637

241-2 241-6																	241-638
241-2 241-6																	241-638


241-3 241-7																	241-639
241-3 241-7																	241-639


241-4			241-8																						241-640
241-4			241-8																						241-640

*Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel

	Figure 7-31: Dual Monochrome 8-Bit Panel Timing
VDP	= Vertical Display Period	= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP	= Vertical Non-Display Period	= (REG[0Ah] bits [5:0]) + 1
HDP	= Horizontal Display Period	= ((REG[04h] bits [6:0]) + 1)*8Ts
HNDP	= Horizontal Non-Display Period	= ((REG[05h] bits [4:0]) + 1)*8Ts

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18

Image 83

Epson S1D13504 manual Dual Monochrome 8-Bit Panel Timing, Fpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0

Contents

Document Number X19A-Q-002-14 Technical ManualThis page Left Blank Customer Support Information This page Left Blank CPU Interface Power Down ModesGeneral Purpose IO pins Memory InterfaceRamdac CPUDocument Number X19A-A-002-18 Hardware Functional SpecificationX19A-A-002-18 Issue Date 01/01/30 Table of Contents Registers Clocking 119 Display Configuration 116Power Save Modes 128 Display BufferThis page Left Blank List of Tables Vancouver Design Center List of Figures Vancouver Design Center Overview Description IntroductionScope Display Support FeaturesMemory Interface CPU InterfacePackage and Pin Display ModesClock Source MiscellaneousLCD Typical System Implementation DiagramsManagement MC68000 Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM Memory Controller Functional Block DiagramBlock Description Functional Block Descriptions Host InterfaceLCD Interface Power SaveLook-Up Table Package type 128 pin surface mount QFP15 Pinout Diagram for S1D13504F00APin Out Package type 128 pin surface mount TQFP15 Pinout Diagram for S1D13504F01APackage type 144 pin surface mount QFP20 Pinout Diagram for S1D13504F02ATS2 Pin DescriptionKey AB0RD/WR# CS#Busclk BS#WAIT# TS2 RESET#RAS# CO1 LCAS# CO1UCAS# CO1 WE# CO1MA9 TS1 LCD Interface Pin Descriptions Clock InputCRT and External Ramdac Interface BLANK# CN3 CRT and Ramdac Interface Pin DescriptionsHrtc VrtcPin # Pin Name Type Driver Description F00A F02A F01A Power SupplySummary of Configuration Options Asym 1Mx16 Multiple Function Pin MappingS1D13504 SH-3 MC68K Bus Generic MPU Pin Names Asym 256Kx1611 LCD, CRT, Ramdac Interface Pin Mapping Symbol Parameter Condition Min Typ Max Units C. CharacteristicsSymbol Parameter Rating Units Bidirectional Pin Capacitance Low Level Output VoltageOutput Leakage Current Output Pin CapacitanceWAIT# CPU Interface Timing 1 SH-3 Interface TimingRD/WR# BS# Symbol Parameter Min Max Units T13 T14 T15 D150read 2 MC68K Bus 1 Interface Timing e.g. MC68000AS# UDS# LDS# D150 valid to DTACK# falling edge read cycle AS# high setup to CLKAS# high to DTACK# high impedance D150 hold from falling edge of DTACK# write cycleT13 T14 T15 3 MC68K Bus 2 Interface Timing e.g. MC68030A200 SIZ10 M/R# AS# DS#D3116 valid to DSACK1# falling edge read cycle D3116 hold from falling edge of DSACK1# write cycleRD0#,RD1# WE0#,WE1# Hi-Z Generic MPU Interface Synchronous TimingBclk A200Low write cycle D150 hold from WE0#, WE1# high write cycle Hi-Z Valid T10 D150read Generic MPU Interface Asynchronous TimingA200 Valid T82 Clock Input Requirements Symbol Parameter Min Typ Max UnitsRAS# CAS# Memory Interface Timing EDO-DRAM Read TimingEDO Dram Read Timing RAS# CAS# WE# EDO-DRAM Write Timing55 t1 + CAS# precharge time 45 t1 T14 Write Data setup time 45 t1 T15 Write Data hold timeEDO-DRAM Read-Write Timing EDO-DRAM Read-Write TimingEDO Dram Read-Write Timing 10 EDO-DRAM CAS Before RAS Refresh Timing EDO-DRAM CAS Before RAS Refresh Timing11 EDO-DRAM Self-Refresh Timing EDO-DRAM Self-Refresh Timing12 FPM-DRAM Read Timing FPM-DRAM Read Timing12 FPM Dram Read Timing 13 FPM-DRAM Write Timing FPM-DRAM Write TimingT14 Write Data setup time 45 t1 T15 Write Data hold time 14 FPM-DRAM Read-Write Timing FPM-DRAM Read-Write Timing45 t1 S1D13504 RAS# precharge time REG22h bits 32 = 01 or 45 t1 FPM-DRAM CAS# Before RAS# Refresh Timing16 FPM-DRAM CBR Self-Refresh Timing FPM-DRAM Self-Refresh TimingFpframe active Display Interface Power-On/Reset TimingMclk Suspend TimingHDP = Single Monochrome 4-Bit Panel TimingVDP = Vndp =Data Timing Sync TimingHDP Single Monochrome 8-Bit Panel TimingVDP Vndp= REG05h bits 40 + 1*8 14 Ts UD30, LD30 setup to Fpshift falling edgeUD30, LD30 hold to Fpshift falling edge = REG05h bits 40 + 1*8 23 Ts23 Single Color 4-Bit Panel Timing Single Color 4-Bit Panel Timing= REG05h bits 40 + 1*8 17 Ts = REG04h bits 60+1*8 1 Ts= REG05h bits 40 + 1*8 26 Ts 25 Single Color 8-Bit Panel Timing Format Single Color 8-Bit Panel Timing FormatFPSHIFT2, Fpshift pulse width high UD30, LD30 setup to FPSHIFT2 rising, Fpshift falling edgeFpline pulse width Fpline period FPSHIFT2 falling edge to Fpline rising edge27 Single Color 8-Bit Panel Timing Format T1min = t3min 9Ts VDP Vndp LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP Hndp Single Color 16-Bit Panel TimingUD70, LD70 hold to Fpshift falling edge UD70, LD70 setup to Fpshift falling edgeFpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Monochrome 8-Bit Panel Timing= REG05h bits 40 + 1*8 8 Ts 33 Dual Color 8-Bit Panel Timing Dual Color 8-Bit Panel Timing= REG05h bits 40 + 1*8 9 Ts 35 Dual Color 16-Bit Panel Timing Dual Color 16-Bit Panel TimingUD70 LD70 = Vertical Display Period = REG09h bits 10, REG08h bits 70 + 12 16-Bit TFT Panel Timing38 TFT A.C. Timing = REG0Ch bits 20+1 lines = REG04h bits 60+1*8 + REG05h bits 40+1*8 Ts= REG07h bits 30+1*8 Ts 39 CRT Timing CRT Timing40 CRT A.C. Timing Dacclk period DACWR# pulse width low External Ramdac Read / Write TimingRead WriteRevision Code Register RegistersRegister Mapping Register DescriptionsTime/256 Cycles Memory Configuration RegistersMemory Configuration Register REG03h MOD Rate Bit Panel/Monitor Configuration RegistersPanel Type Register MOD Rate RegisterHRTC/FPLINE Start Position Register Horizontal Display Width RegisterHorizontal Non-Display Period Register Hrtc Fpline HRTC/FPLINE Pulse Width RegisterVertical Display Height Register Vrtc Fpframe Vertical Non-Display Period RegisterVRTC/FPFRAME Start Position Register Vrtc Polarity VRTC/FPFRAME Pulse Width RegisterREG0Ch Fpframe VrtcEven Scan Only Display Configuration RegistersDisplay Mode Register Simultaneous Display Option Select BitsNumber of Bits-Per-Pixel Selection Screen 1 Display Start Address Register Screen 1 Line Compare RegisterMemory Address Offset Register Screen 2 Display Start Address Register 0 RWScreen 2 Display Start Address Register Number of Bits-Per-Pixel Screen 2 Pixel Panning Bits Used Clock Configuration RegisterClock Configuration Register Pixel Panning RegisterMiscellaneous Registers Power Save Configuration RegistersPower Save Configuration Register Miscellaneous Disable RegisterMD9 MD8 MD Configuration Readback RegisterGpio Configuration Register REG1Dh MD15 MD14 MD13 MD12 MD11 MD10Vancouver Design Center REG1Fh GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config Gpio Status / Control Register GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin Control IO Status Gpio Status / Control RegisterREG21h GPOMinimum Random Cycle Width t RC Performance Enhancement RegisterREG22h EDO Read RC Timing RAS# to REG22h BitsRAS# Precharge Width t RP RAS# to CAS# Delay tRCDOptimal Dram Timing REG22h BitLook-Up Table Address Register RGB Index Bits Look-Up Table Access Pointer SequenceLook-Up Table Registers REG27h Red Bank Blue Bank Green Bank Select Bit Look-Up Table Data RegisterLook-Up Table Bank Select Register REG26h LUT Data BitRamdac Pixel Read Mask Register Ramdac Read Mode Address RegisterRamdac Write Mode Address Register External Ramdac Control RegistersREG2Eh or REG2Fh Ramdac Palette Data Register512K byte Memory AB200 Display BufferHalf Frame Buffer Image BufferDisplay Mode Data Format Display Configuration15/16 Bit-Per-Pixel Format Memory Organization Image Buffer Image ManipulationDisplay Maximum Pclk Allowed Bpp 16 bpp ClockingMaximum Mclk Pclk Ratios Display typeMHz Frame Rate Calculation= Pclk Speed Grade Bpp Clock Hndpt s PanelFPM-DRAM Gray Shade Display Modes Bit-Per-Pixel ModeDisplay Mode Bit Wide Look-Up Table Look-Up Table ArchitectureBit-Per-Pixel Mode Color Display Modes Bit-Per-Pixel Color ModeBank Selected Bank Entry Bit Red data output Logic Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110 Color Data Format Red Look-Up Table Software Suspend Power Save ModesHardware Suspend Pin State Pins Normal Software Hardware Active Suspend Power Save Mode Function SummaryPin States in Power Save Modes Power Save Mode PSMQFP15 128 pin Unit mm Mechanical Data14.1 QFP15-128 S1D13504F00A ±0.2 TQFP15-128 S1D13504F01ATQFP15 128 pin Unit mm 125 QFP20-144 S1D13504F02AQFP20 144 pin Unit mm Document Number X19A-G-002-07 Programming Notes and ExamplesThis page Left Blank Advanced Techniques LCD Power Sequencing and Power Save ModesIntroduction Programming the S1D13504 Registers Appendix a Supported Panel Values CRT ConsiderationsIdentifying the S1D13504 Hardware Abstraction Layer HAL Sample CodeInitializing the S1D13504 Registers This page Left Blank Introduction 3 REG02 bit 1 Dual/Single Panel Type Programming the S1D13504 Registers2 REG22 bits 7-2 Performance Enhancement Register Register Initialization Initialization Sequence 4 REG1B bit 0 Half Frame Buffer Disable5 REG23 Display Fifo Operation Description Initialization ExampleInitializing the S1D13504 Registers Disabling the Half Frame Buffer Sequence Re-Programming RegistersPixel Bit Display Buffer LocationBit Bit Red Bit Green Bit Blue Bit Memory Organization for Eight Bit-per-pixel 256 ColorsBit Reserved Red Bit Green Bit Blue Bit Memory Organization for 15 Bit-per-pixel 32768 ColorsMemory Organization for 16 Bit-per-pixel 65536 Colors REG27h Look-Up Table Bank Register Read/Write Look-Up Table LUTREG24h Look-Up Table Address Register Read/Write REG26h Look-Up Table Data Register Read/WriteBank Select Bits Bank Look-Up Table ConfigurationsLook-Up Table Organization Address Red Green Blue Recommended LUT Values for 1 bpp Color ModeRecommended LUT Values for 2 bpp Color Mode Color Modes11 Recommended LUT Values For 8 bpp Color Mode Pixel Value Color 12 Examples of 256 Pixel Colors Using Linear LUTGray Shade Modes 13 Recommended LUT Values for 1 bpp Gray ShadesLUT Address Green LUT Data 14 Recommended LUT Values for 2 bpp Gray Shades15 Recommended LUT Values for 8 bpp Gray Shade Bpp Gray Shade Virtual Display Advanced Technique sREG17h Memory Address Offset Register RegistersExamples REG16h Memory Address Offset RegisterPanning and Scrolling Active Pixel Pan Bits Number of Pixels Panned Using Start AddressExample 4 Panning Right and Left REG0F Screen 1 Line Compare Register Split ScreenREG0E Screen 1 Line Compare Register Line Compare BitREG15h Screen 2 Display Start Address Register REG13h Screen 2 Display Start Address RegisterREG14h Screen 2 Display Start Address Register Display Mode Register LCD Power Sequencing and Power Save ModesIntroduction to LCD Power Sequencing Introduction to Power Save ModesSuspend Sequencing Suspend Enable SequenceShortening the 128 Frame delay using Software Suspend Shortening the 128 Frame Delay using Hardware SUSPEND#LCD Enable / Disable using Manual Control Suspend Disable SequenceLCD Enable/Disable Sequencing Reg0D bit LCD Enable / Disable using Power Save ModesRamdac Register Mapping for Little/Big-Endian CRT ConsiderationsIntroduction CRT OnlyRelated Register Data for CRT Only Simultaneous DisplayAddress Address Register 640X480@75Hz 640X480@60Hz Related register data for Simultaneous DisplayIdentifying the S1D13504 Initialization Int seDeRegisterDeviceint device Hardware Abstraction Layer HALAPI for 13504HAL Int seInitHalvoid Int seGetIdint device, Byte *pIdInt seValidStdDeviceint device Int seSetInitint deviceInt seValidRegisteredDeviceint device Int seGetLinearDispAddrint device, Dword *pDispLogicalAddr Int seGetBitsPerPixelint device, Byte *pBitsPerPixelInt seGetBytesPerScanlineint device, int *pBytes Int seGetLastUsableByteint device, Dword *pLastByteInt seReadDisplayWordint device, Dword offset, Word *pWord Int seGetScreenSizeint device, int *width, int *heightInt seReadDisplayByteint device, Dword offset, Byte *pByte Int seSplitInitint device, Dword Scrn1Addr, Dword Scrn2Addr Int seSetBitsPerPixelint device, Byte BitsPerPixelInt seVirtMoveint device, Byte WhichScreen, int x, int y Int seVirtInitint device, int xVirt, long *yVirtVancouver Design Center Int seGetLutint device, Byte *pLut Color Manipulation Int seGetDacint device, Byte *pDacInt seGetDacEntryint device, Byte index, Byte *pEntry Int seSetDacEntryint device, Byte index, Byte *pEntry Int seGetLutEntryint device, Byte index, Byte *pEntryInt seSetDacint device, Byte *pDac Int seSetLutEntryint device, Byte index, Byte *pEntry Int seSetLutint device, Byte *pLutInt seDrawTextint device, char *fmt Int sePutcint device, int ch Int seGetcharvoidInt sePutcharint ch Int seSetRegint device, int index, Byte val Miscellaneous Int seDelayint device, Dword SecondsInt seSetPixelint device, int x, int y, Dword color Word seRotateByteRightBYTE val, Byte bits Word seRotateByteLeftBYTE val, Byte bitsSample Code Sample code using 13504HAL APISample code without using 13504HAL API Vancouver Design Center Pclk To arrive at the frame rate closest to the desired Words Fifo Passive Dual Panel Appendix a Supported Panel ValuesSupported Panel Values Passive Single PanelTFT 16-Bit Register Single TFT Panel01/02/02 Number of Bits/Pixel Document Number X19A-B-001-04 13504CFG.EXE Configuration ProgramVancouver Design Center X19A-B-001-04 13504CFG.EXE Program Requirements Script Mode Interactive ModeThis page Left Blank 13504CFG View Menu This page Left Blank 13504CFG.EXE Usage InstallationProgram Requirements Script Mode 13504CFG Menu Bar Interactive ModeMaking 13504CFG Menu Selections Files Menu View Menu 13504CFG Current Configuration Device Menu Panel Edit Panel Setup CRT Edit CRT Setup Advanced Memory Edit Advanced Memory Setup Power Management Edit Power Setup Lookup Table LUT Edit LUT Setup Setup Help Menu Sample Program Messages CommentsThis page Left Blank Document Number X19A-B-002-05 13504SHOW Demonstration ProgramThis page Left Blank S1D13504 Supported Evaluation Platforms 13504SHOWProgram Messages Error Too many devices registeredDocument Number X19A-B-003-05 13504SPLT Display UtilityThis page Left Blank 13504SPLT 13504SPLT Example Comments This page Left Blank Document Number X19A-B-004-05 13504VIRT Display UtilityS1D13504 13504VIRT Display Utility X19A-B-004-05 13504VIRT 13504VIRT Example Comments This page Left Blank Document Number X19A-B-005-05 13504PLAY Diagnostic UtilityThis page Left Blank 13504PLAY Reads/writes the registers Scripting 13504PLAY ExampleComments Document Number X19A-B-006-04 13504BMP Demonstration ProgramThis page Left Blank 13504BMP Program Messages Document Number X19A-B-007-04 13504PWR Software Suspend Power Sequencing UtilityX19A-B-007-04 Issue Date 01/02/01 13504PWR Selects software suspend Error Unknown command line argument This page Left Blank Document Number X19A-B-008-02 13504DCFG Configuration ProgramThis page Left Blank Table of Contents This page Left Blank Clocks Tab Panel Tab List of FiguresThis page Left Blank Usage Installation13504DCFG 13504DCFG Configuration Tabs General Tab General TabMemory Tab Memory TabClocks Tab Clocks TabCRT Mclkpclk Clocks TabClki LCD MclkpclkPanel Tab Panel TabVRTC/FPFRAME Panel TabSTN/TFT HRTC/FPLINECRT Tab CRT TabInitializes the registers based on the default mode Defaults TabDefaults Tab Select the default display device. Three display modes LCDRegisters Tab Registers TabMiscellaneous Flags Tab Miscellaneous Flags TabSaving to a File Comments Resolution Frame Rate Hz Pclk MHz Supported Dram TypesDocument Number X19A-E-001-04 Windows CE Display DriversX19A-E-001-04 Windows Version DIP SwitchProgram Requirements Example Driver BuildsWith this line Build For Cepc If CEPCDDIVGA2BPP Epson Research and Development Installation for Cepc Environment Example InstallationInstallation for Hitachi D9000 and Etma ODO Comments This page Left Blank Document Number X19A-E-002-03 Wind River WindML v2.0 Display DriversX19A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers Make CPU=PENTIUM ugl Building a WindML v2.0 Display DriverEpson Research and Development This page Left Blank Document Number X19A-E-003-02 Wind River UGL v1.2 Display DriversX19A-E-003-02 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Document Number X19A-G-004-06 S1D13504 X19A-G-004-06 Issue Date 01/02/02 Parts List Schematic Diagrams Installation and ConfigurationThis page Left Blank S1D13504B00C Schematic Diagram 1 of 6 This page Left Blank Features Host Bus Selection Installation and ConfigurationConfiguration DIP Switch Settings Jumper SettingsLCD / Ramdac Interface Pin Mapping LCD Signal Connector J6Connector Comments Pin No CPU / BUS Interface Connector PinoutsCPU/BUS Connector H1 Pinout CPU/BUS Connector H2 Pinout DB150 D150 D3116 WE1# Host Bus Interface Pin MappingISA Bus Support Technical DescriptionClock Input Support Non-ISA Bus SupportDram Support Decode LogicExternal Cmos Ramdac Support Monochrome LCD Panel SupportColor Passive LCD Panel Support Color TFT LCD Panel SupportAdjustable LCD Panel Negative Power Supply Power Save ModesCore VDD Power Supply IO VDD Power Supply15 CPU/Bus Interface Header Strips Schematic NotesItem # Qty/board Designation Part Value Description Parts ListTexas Instrument PAL 24 pin DIP package/socketed TIBPAL22V10-15BCNTDiagrams SchematicS1D13504B00C Schematic Diagram 2 Rev.1.0 S1D13504B00C Schematic Diagram 4 Diagram 5 S1D13504B00C Schematic Diagram 6 This page Left Blank Document Number X19A-G-003-05 S5U13504-D9000S5U13504-D9000 X19A-G-003-05 Issue Date 01/02/02 D9000 Specifics Introduction FeaturesThis page Left Blank S5U13504-D9000 Perspective View This page Left Blank Reference Display Buffer S1D13504 Color Graphics LCD ControllerLCD Display Support LCD Interface Pin Mapping LCD Connector PinoutCRT Support Adjustable LCD Bias Power SupplyD9000 Specifics Interface SignalsConnector Pinout for Channel A6 and A7 Interface SignalsDC12V Connector Pinout for Channel A7GND Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ BS# GND Connectors Pinout for Channel A6Channel A6 Pin # Fpga Signal S1D13504 Signal SmXY Channel A6 Pin # Fpga Signal S1D13504 Signal SmZ Makefpga file Board DimensionsBus Interface Timing Memory Address CS#, M/R# DecodeItem # Qty Reference Part Description Parts ListSchematic S5U13504-D9000 Schematic Diagram 2 S5U13504-D9000 Schematic Diagram 3 D9000 Component Placement PCB Layout Component PlacementS5U13504-D9000 Perspective View Perspective ViewDocument Number X19A-G-006-04 Power ConsumptionS1D13504 Power Consumption X19A-G-006-04 S1D13504 Power Consumption Conditions S1D13504 Total Power ConsumptionSummary Document Number X19A-G-005-08 Interfacing to the Philips Mips PR31500/PR31700 ProcessorThis page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank List of Tables S1D13504 to PR31500/PR31700 Connection using One IT8368EThis page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13504 Generic MPU Pin Names WAIT# RESET#S1D13504 Host Bus Interface Generic MPU Host Bus Interface Pin MappingGeneric MPU Host Bus Interface Signals Hardware Description Direct Connection to the Philips PR31500/PR31700Memory Mapping and Aliasing MD3 MD4 S1D13504 ConfigurationMD1 MD2 Hardware Description-Using One IT8368E System Design Using the IT8368E PC Card BufferLogic Chip SelectVancouver Design Center PR31500/PR31700 S1D13504 Hardware Description-Using Two IT8368E’sIT8368E Configuration IT8368E Uses PC Card Slot # Philips Address Size Function TX3912 Address Size Function CARDnIOEN=0 CARDnIOEN=1S1D13504 Configuration using the IT8368E Software Document Sources ReferencesDocuments ITE IT8368E Technical SupportEpson LCD/CRT Controllers S1D13504 Philips Mips PR31500/PR31700 ProcessorThis page Left Blank Document Number X19A-G-007-07 Interfacing to the NEC VR4102 MicroprocessorX19A-G-007-07 Issue Date 01/02/02 Introduction Interfacing to the NEC VR4102 This page Left Blank NEC VR4102 Read/Write Cycles This page Left Blank Introduction Overview Interfacing to the NEC VR4102NEC VR4102 System Bus Lcdrdy LCD Memory Access CyclesS1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Decode Logic VR4102 to S1D13504 InterfaceRead/Write Generic bus interface e.g. MPC821, ISA bus interface S1D13504 Hardware ConfigurationWrite NEC VR4102 ConfigurationNEC Signals Cycle S1D13504 Signals WR#Software References Japan North America Taiwan, R.O.C NEC Electronics Inc. VR4102This page Left Blank Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A-G-011-07 Issue Date 01/02/02 S1D13504 Bus Interface This page Left Blank List of Tables This page Left Blank Introduction Normal Non-Burst Bus Transactions Interfacing to the MCF5307MCF5307 System Bus MCF5307 Memory Read Cycle Burst Cycles Chip-Select ModuleS1D13504 Bus Interface Generic MPU Host Bus Interface Signals Hardware Connections MCF5307 To S1D13504 InterfaceS1D13504 Configuration Settings Memory/Register Mapping MCF5307 Chip Select ConfigurationSoftware Motorola Inc. Motorola Literature Distribution Center, 800 Motorola MCF5307 Processor S1D13504 Color Graphics LCD / CRT Controller X19A-G-013-02 Issue Date 01/02/02 Introduction Interfacing to the MC68328 This page Left Blank Generic MPU Host Bus Interface Pin Mapping This page Left Blank Introduction 68328 System Bus Interfacing to the MC68328S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals MC68328 To S1D13504 Interface Busclk RESET#CSB3 Dtack UWE LWE CLK0 MD7 MD6Option Memory Selection MC68328 Chip Select ConfigurationSoftware References Motorola MC68328 Processor This page Left Blank Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-05 Issue Date 01/02/02 Introduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction MPC821 Bus Overview Interfacing to the MPC821MPC8xx System Bus Power PC Memory Read Cycle Power PC Memory Write Cycle General-Purpose Chip Select Module Gpcm Memory Controller ModuleUser-Programmable Machine UPM S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of MPC821 to S1D13504 Interface MPC821 to S1D13504 InterfaceAB6 AB9AB8 AB7WE0 SresetSysclk CS4S1D13504 Hardware Configuration Register/Memory Mapping MPC821 Chip Select ConfigurationSource Code Test SoftwareEpson Research and Development Software References Motorola MPC821 Processor Document Number X19A-G-009-05 Interfacing to the PC Card BusThis page Left Blank Introduction Interfacing to the PC Card Bus This page Left Blank PC Card Read Cycle This page Left Blank Introduction PC Card Overview Memory Access CyclesInterfacing to the PC Card Bus PC Card System BusPC Card Read Cycle S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of PC Card to S1D13504 Interface PC Card to S1D13504 InterfaceGeneric MPU SH-3Equations PAL EquationsSoftware PCMCIA/JEIDA, PC Card Standard -- March Pcmcia PC Card StandardThis page Left Blank Document Number X19A-G-012-04 Interfacing to the Toshiba Mips TX3912 ProcessorThis page Left Blank Direct Connection to the Toshiba TX3912 This page Left Blank S1D13504 to TX3912 Connection using One IT8368E This page Left Blank Introduction Interfacing to the TX3912 S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Direct Connection to the Toshiba TX3912 Memory Mapping and Aliasing S1D13504 Hardware Configuration System Design Using the IT8368E PC Card Buffer S1D13504 to TX3912 Connection using One IT8368E Hardware Description-Using Two IT8368E’s S1D13504 to TX3912 Connection using Two IT8368E IT8368E Configuration 64Mb Card 2 Memory 64Mb64Mb Card 2 Attribute 64Mb Card 1 MemoryS1D13504 Configuration Software References Toshiba Mips TX3912 Processor ITE IT8368E This page Left Blank