Document Number X19A-Q-002-14
Technical Manual
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Customer Support Information
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General Purpose IO pins
Power Down Modes
Memory Interface
CPU Interface
Ramdac
CPU
Document Number X19A-A-002-18
Hardware Functional Specification
X19A-A-002-18 Issue Date 01/01/30
Table of Contents
Registers
Power Save Modes 128
Display Configuration 116
Display Buffer
Clocking 119
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List of Tables
Vancouver Design Center
List of Figures
Vancouver Design Center
Introduction
Scope
Overview Description
Memory Interface
Features
CPU Interface
Display Support
Clock Source
Display Modes
Miscellaneous
Package and Pin
LCD
Typical System Implementation Diagrams
Management MC68000
Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM
Block Description
Functional Block Diagram
Functional Block Descriptions Host Interface
Memory Controller
Power Save
Look-Up Table
LCD Interface
Pinout Diagram for S1D13504F00A
Pin Out
Package type 128 pin surface mount QFP15
Package type 128 pin surface mount TQFP15
Pinout Diagram for S1D13504F01A
Package type 144 pin surface mount QFP20
Pinout Diagram for S1D13504F02A
Key
Pin Description
AB0
TS2
Busclk
CS#
BS#
RD/WR#
WAIT# TS2
RESET#
UCAS# CO1
LCAS# CO1
WE# CO1
RAS# CO1
MA9 TS1
LCD Interface Pin Descriptions
Clock Input
CRT and External Ramdac Interface
Hrtc
CRT and Ramdac Interface Pin Descriptions
Vrtc
BLANK# CN3
Pin # Pin Name Type Driver Description F00A F02A F01A
Power Supply
Summary of Configuration Options
S1D13504 SH-3 MC68K Bus Generic MPU Pin Names
Multiple Function Pin Mapping
Asym 256Kx16
Asym 1Mx16
11 LCD, CRT, Ramdac Interface Pin Mapping
C. Characteristics
Symbol Parameter Rating Units
Symbol Parameter Condition Min Typ Max Units
Output Leakage Current
Low Level Output Voltage
Output Pin Capacitance
Bidirectional Pin Capacitance
CPU Interface Timing 1 SH-3 Interface Timing
RD/WR# BS#
WAIT#
Symbol Parameter Min Max Units
2 MC68K Bus 1 Interface Timing e.g. MC68000
AS# UDS# LDS#
T13 T14 T15 D150read
AS# high to DTACK# high impedance
AS# high setup to CLK
D150 hold from falling edge of DTACK# write cycle
D150 valid to DTACK# falling edge read cycle
A200 SIZ10 M/R#
3 MC68K Bus 2 Interface Timing e.g. MC68030
AS# DS#
T13 T14 T15
D3116 valid to DSACK1# falling edge read cycle
D3116 hold from falling edge of DSACK1# write cycle
Bclk
Generic MPU Interface Synchronous Timing
A200
RD0#,RD1# WE0#,WE1# Hi-Z
Low write cycle D150 hold from WE0#, WE1# high write cycle
Generic MPU Interface Asynchronous Timing
A200 Valid
Hi-Z Valid T10 D150read
T82
Clock Input Requirements
Symbol Parameter Min Typ Max Units
RAS# CAS#
Memory Interface Timing EDO-DRAM Read Timing
EDO Dram Read Timing
RAS# CAS# WE#
EDO-DRAM Write Timing
55 t1 + CAS# precharge time 45 t1
T14 Write Data setup time 45 t1 T15 Write Data hold time
EDO-DRAM Read-Write Timing
EDO-DRAM Read-Write Timing
EDO Dram Read-Write Timing
10 EDO-DRAM CAS Before RAS Refresh Timing
EDO-DRAM CAS Before RAS Refresh Timing
11 EDO-DRAM Self-Refresh Timing
EDO-DRAM Self-Refresh Timing
12 FPM-DRAM Read Timing
FPM-DRAM Read Timing
12 FPM Dram Read Timing
13 FPM-DRAM Write Timing
FPM-DRAM Write Timing
T14 Write Data setup time 45 t1 T15 Write Data hold time
14 FPM-DRAM Read-Write Timing
FPM-DRAM Read-Write Timing
45 t1 S1D13504
RAS# precharge time REG22h bits 32 = 01 or 45 t1
FPM-DRAM CAS# Before RAS# Refresh Timing
16 FPM-DRAM CBR Self-Refresh Timing
FPM-DRAM Self-Refresh Timing
Fpframe active
Display Interface Power-On/Reset Timing
Mclk
Suspend Timing
VDP =
Single Monochrome 4-Bit Panel Timing
Vndp =
HDP =
Data Timing
Sync Timing
VDP
Single Monochrome 8-Bit Panel Timing
Vndp
HDP
UD30, LD30 hold to Fpshift falling edge
UD30, LD30 setup to Fpshift falling edge
= REG05h bits 40 + 1*8 23 Ts
= REG05h bits 40 + 1*8 14 Ts
23 Single Color 4-Bit Panel Timing
Single Color 4-Bit Panel Timing
= REG04h bits 60+1*8 1 Ts
= REG05h bits 40 + 1*8 26 Ts
= REG05h bits 40 + 1*8 17 Ts
25 Single Color 8-Bit Panel Timing Format
Single Color 8-Bit Panel Timing Format
Fpline pulse width Fpline period
UD30, LD30 setup to FPSHIFT2 rising, Fpshift falling edge
FPSHIFT2 falling edge to Fpline rising edge
FPSHIFT2, Fpshift pulse width high
27 Single Color 8-Bit Panel Timing Format
T1min = t3min 9Ts
VDP Vndp LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP Hndp
Single Color 16-Bit Panel Timing
UD70, LD70 hold to Fpshift falling edge
UD70, LD70 setup to Fpshift falling edge
Fpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
Dual Monochrome 8-Bit Panel Timing
= REG05h bits 40 + 1*8 8 Ts
33 Dual Color 8-Bit Panel Timing
Dual Color 8-Bit Panel Timing
= REG05h bits 40 + 1*8 9 Ts
35 Dual Color 16-Bit Panel Timing
Dual Color 16-Bit Panel Timing
UD70 LD70
= Vertical Display Period = REG09h bits 10, REG08h bits 70 +
12 16-Bit TFT Panel Timing
38 TFT A.C. Timing
= REG04h bits 60+1*8 + REG05h bits 40+1*8 Ts
= REG07h bits 30+1*8 Ts
= REG0Ch bits 20+1 lines
39 CRT Timing
CRT Timing
40 CRT A.C. Timing
Dacclk period
Read
External Ramdac Read / Write Timing
Write
DACWR# pulse width low
Register Mapping
Registers
Register Descriptions
Revision Code Register
Memory Configuration Registers
Memory Configuration Register
Time/256 Cycles
Panel Type Register
Panel/Monitor Configuration Registers
MOD Rate Register
REG03h MOD Rate Bit
Horizontal Display Width Register
Horizontal Non-Display Period Register
HRTC/FPLINE Start Position Register
HRTC/FPLINE Pulse Width Register
Vertical Display Height Register
Hrtc Fpline
Vertical Non-Display Period Register
VRTC/FPFRAME Start Position Register
Vrtc Fpframe
REG0Ch
VRTC/FPFRAME Pulse Width Register
Fpframe Vrtc
Vrtc Polarity
Display Mode Register
Display Configuration Registers
Simultaneous Display Option Select Bits
Even Scan Only
Number of Bits-Per-Pixel Selection
Screen 1 Display Start Address Register
Screen 1 Line Compare Register
Screen 2 Display Start Address Register 0 RW
Screen 2 Display Start Address Register
Memory Address Offset Register
Clock Configuration Register
Clock Configuration Register
Pixel Panning Register
Number of Bits-Per-Pixel Screen 2 Pixel Panning Bits Used
Power Save Configuration Register
Power Save Configuration Registers
Miscellaneous Disable Register
Miscellaneous Registers
Gpio Configuration Register
MD Configuration Readback Register
REG1Dh MD15 MD14 MD13 MD12 MD11 MD10
MD9 MD8
Vancouver Design Center
REG1Fh GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config
Gpio Status / Control Register
REG21h
Gpio Status / Control Register
GPO
GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin Control IO Status
REG22h EDO Read RC Timing RAS# to
Performance Enhancement Register
REG22h Bits
Minimum Random Cycle Width t RC
Optimal Dram Timing
RAS# to CAS# Delay tRCD
REG22h Bit
RAS# Precharge Width t RP
RGB Index Bits Look-Up Table Access Pointer Sequence
Look-Up Table Registers
Look-Up Table Address Register
Look-Up Table Bank Select Register
Look-Up Table Data Register
REG26h LUT Data Bit
REG27h Red Bank Blue Bank Green Bank Select Bit
Ramdac Write Mode Address Register
Ramdac Read Mode Address Register
External Ramdac Control Registers
Ramdac Pixel Read Mask Register
REG2Eh or REG2Fh
Ramdac Palette Data Register
512K byte Memory AB200
Display Buffer
Half Frame Buffer
Image Buffer
Display Mode Data Format
Display Configuration
15/16 Bit-Per-Pixel Format Memory Organization
Image Manipulation
Display
Image Buffer
Maximum Mclk Pclk Ratios
Clocking
Display type
Maximum Pclk Allowed Bpp 16 bpp
= Pclk
Frame Rate Calculation
Speed Grade Bpp Clock Hndpt s Panel
MHz
FPM-DRAM
Display Mode Bit Wide Look-Up Table
Bit-Per-Pixel Mode
Look-Up Table Architecture
Gray Shade Display Modes
Bit-Per-Pixel Mode
Color Display Modes
Bit-Per-Pixel Color Mode
Bank Selected Bank Entry Bit Red data output Logic
Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110
Color Data Format Red Look-Up Table
Power Save Modes
Hardware Suspend
Software Suspend
Pin States in Power Save Modes
Power Save Mode Function Summary
Power Save Mode PSM
Pin State Pins Normal Software Hardware Active Suspend
Mechanical Data
14.1 QFP15-128 S1D13504F00A
QFP15 128 pin Unit mm
TQFP15-128 S1D13504F01A
TQFP15 128 pin Unit mm
±0.2
QFP20-144 S1D13504F02A
QFP20 144 pin Unit mm
125
Document Number X19A-G-002-07
Programming Notes and Examples
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LCD Power Sequencing and Power Save Modes
Introduction Programming the S1D13504 Registers
Advanced Techniques
Identifying the S1D13504 Hardware Abstraction Layer HAL
CRT Considerations
Sample Code
Appendix a Supported Panel Values
Initializing the S1D13504 Registers
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Introduction
Programming the S1D13504 Registers
2 REG22 bits 7-2 Performance Enhancement Register
3 REG02 bit 1 Dual/Single Panel Type
4 REG1B bit 0 Half Frame Buffer Disable
5 REG23 Display Fifo
Register Initialization Initialization Sequence
Initialization Example
Initializing the S1D13504 Registers
Operation Description
Disabling the Half Frame Buffer Sequence
Re-Programming Registers
Display Buffer Location
Bit
Pixel Bit
Bit Red Bit Green Bit Blue Bit
Memory Organization for Eight Bit-per-pixel 256 Colors
Memory Organization for 15 Bit-per-pixel 32768 Colors
Memory Organization for 16 Bit-per-pixel 65536 Colors
Bit Reserved Red Bit Green Bit Blue Bit
REG24h Look-Up Table Address Register Read/Write
Look-Up Table LUT
REG26h Look-Up Table Data Register Read/Write
REG27h Look-Up Table Bank Register Read/Write
Bank Select Bits
Look-Up Table Configurations
Look-Up Table Organization
Bank
Recommended LUT Values for 2 bpp Color Mode
Recommended LUT Values for 1 bpp Color Mode
Color Modes
Address Red Green Blue
11 Recommended LUT Values For 8 bpp Color Mode
Gray Shade Modes
12 Examples of 256 Pixel Colors Using Linear LUT
13 Recommended LUT Values for 1 bpp Gray Shades
Pixel Value Color
14 Recommended LUT Values for 2 bpp Gray Shades
15 Recommended LUT Values for 8 bpp Gray Shade
LUT Address Green LUT Data
Bpp Gray Shade
Virtual Display
Advanced Technique s
Examples
Registers
REG16h Memory Address Offset Register
REG17h Memory Address Offset Register
Panning and Scrolling
Active Pixel Pan Bits
Number of Pixels Panned Using Start Address
Example 4 Panning Right and Left
REG0E Screen 1 Line Compare Register
Split Screen
Line Compare Bit
REG0F Screen 1 Line Compare Register
REG13h Screen 2 Display Start Address Register
REG14h Screen 2 Display Start Address Register
REG15h Screen 2 Display Start Address Register
Introduction to LCD Power Sequencing
LCD Power Sequencing and Power Save Modes
Introduction to Power Save Modes
Display Mode Register
Shortening the 128 Frame delay using Software Suspend
Suspend Enable Sequence
Shortening the 128 Frame Delay using Hardware SUSPEND#
Suspend Sequencing
LCD Enable/Disable Sequencing Reg0D bit
Suspend Disable Sequence
LCD Enable / Disable using Power Save Modes
LCD Enable / Disable using Manual Control
Introduction
CRT Considerations
CRT Only
Ramdac Register Mapping for Little/Big-Endian
Related Register Data for CRT Only
Simultaneous Display
Address
Address
Register 640X480@75Hz 640X480@60Hz
Related register data for Simultaneous Display
Identifying the S1D13504
Hardware Abstraction Layer HAL
API for 13504HAL
Initialization Int seDeRegisterDeviceint device
Int seInitHalvoid
Int seGetIdint device, Byte *pId
Int seSetInitint device
Int seValidRegisteredDeviceint device
Int seValidStdDeviceint device
Int seGetBytesPerScanlineint device, int *pBytes
Int seGetBitsPerPixelint device, Byte *pBitsPerPixel
Int seGetLastUsableByteint device, Dword *pLastByte
Int seGetLinearDispAddrint device, Dword *pDispLogicalAddr
Int seGetScreenSizeint device, int *width, int *height
Int seReadDisplayByteint device, Dword offset, Byte *pByte
Int seReadDisplayWordint device, Dword offset, Word *pWord
Int seSplitInitint device, Dword Scrn1Addr, Dword Scrn2Addr
Int seSetBitsPerPixelint device, Byte BitsPerPixel
Int seVirtMoveint device, Byte WhichScreen, int x, int y
Int seVirtInitint device, int xVirt, long *yVirt
Vancouver Design Center
Color Manipulation Int seGetDacint device, Byte *pDac
Int seGetDacEntryint device, Byte index, Byte *pEntry
Int seGetLutint device, Byte *pLut
Int seGetLutEntryint device, Byte index, Byte *pEntry
Int seSetDacint device, Byte *pDac
Int seSetDacEntryint device, Byte index, Byte *pEntry
Int seSetLutEntryint device, Byte index, Byte *pEntry
Int seSetLutint device, Byte *pLut
Int seDrawTextint device, char *fmt
Int seGetcharvoid
Int sePutcharint ch
Int sePutcint device, int ch
Miscellaneous Int seDelayint device, Dword Seconds
Int seSetPixelint device, int x, int y, Dword color
Int seSetRegint device, int index, Byte val
Word seRotateByteRightBYTE val, Byte bits
Word seRotateByteLeftBYTE val, Byte bits
Sample Code
Sample code using 13504HAL API
Sample code without using 13504HAL API
Vancouver Design Center
Pclk
To arrive at the frame rate closest to the desired
Words
Fifo
Supported Panel Values
Appendix a Supported Panel Values
Passive Single Panel
Passive Dual Panel
TFT 16-Bit Register Single
TFT Panel
01/02/02
Number of Bits/Pixel
Document Number X19A-B-001-04
13504CFG.EXE Configuration Program
Vancouver Design Center
X19A-B-001-04
13504CFG.EXE Program Requirements
Script Mode Interactive Mode
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13504CFG View Menu
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13504CFG.EXE
Installation
Program Requirements
Usage
Script Mode
13504CFG Menu Bar
Interactive Mode
Making 13504CFG Menu Selections
Files Menu
View Menu
13504CFG Current Configuration
Device Menu
Panel
Edit Panel Setup
CRT
Edit CRT Setup
Advanced Memory
Edit Advanced Memory Setup
Power Management
Edit Power Setup
Lookup Table LUT
Edit LUT Setup
Setup
Help Menu
Sample Program Messages
Comments
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Document Number X19A-B-002-05
13504SHOW Demonstration Program
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S1D13504 Supported Evaluation Platforms
13504SHOW
Program Messages
Error Too many devices registered
Document Number X19A-B-003-05
13504SPLT Display Utility
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13504SPLT
13504SPLT Example
Comments
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Document Number X19A-B-004-05
13504VIRT Display Utility
S1D13504 13504VIRT Display Utility X19A-B-004-05
13504VIRT
13504VIRT Example
Comments
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Document Number X19A-B-005-05
13504PLAY Diagnostic Utility
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13504PLAY
Reads/writes the registers
Scripting
13504PLAY Example
Comments
Document Number X19A-B-006-04
13504BMP Demonstration Program
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13504BMP
Program Messages
Document Number X19A-B-007-04
13504PWR Software Suspend Power Sequencing Utility
X19A-B-007-04 Issue Date 01/02/01
13504PWR
Selects software suspend
Error Unknown command line argument
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Document Number X19A-B-008-02
13504DCFG Configuration Program
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Table of Contents
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Clocks Tab Panel Tab
List of Figures
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Installation
13504DCFG
Usage
13504DCFG Configuration Tabs
General Tab
General Tab
Memory Tab
Memory Tab
Clocks Tab
Clocks Tab
Clki
Clocks Tab
LCD Mclkpclk
CRT Mclkpclk
Panel Tab
Panel Tab
STN/TFT
Panel Tab
HRTC/FPLINE
VRTC/FPFRAME
CRT Tab
CRT Tab
Defaults Tab
Defaults Tab
Select the default display device. Three display modes LCD
Initializes the registers based on the default mode
Registers Tab
Registers Tab
Miscellaneous Flags Tab
Miscellaneous Flags Tab
Saving to a File
Comments
Resolution Frame Rate Hz Pclk MHz Supported Dram Types
Document Number X19A-E-001-04
Windows CE Display Drivers
X19A-E-001-04
Program Requirements
DIP Switch
Example Driver Builds
Windows Version
With this line
Build For Cepc
If CEPCDDIVGA2BPP
Epson Research and Development
Example Installation
Installation for Hitachi D9000 and Etma ODO
Installation for Cepc Environment
Comments
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Document Number X19A-E-002-03
Wind River WindML v2.0 Display Drivers
X19A-E-002-03 Issue Date 01/04/06
Wind River WindML v2.0 Display Drivers
Make CPU=PENTIUM ugl
Building a WindML v2.0 Display Driver
Epson Research and Development
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Document Number X19A-E-003-02
Wind River UGL v1.2 Display Drivers
X19A-E-003-02
Wind River UGL v1.2 Display Drivers
Building a UGL v1.2 Display Driver
Epson Research and Development
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Document Number X19A-G-004-06
S1D13504 X19A-G-004-06 Issue Date 01/02/02
Parts List Schematic Diagrams
Installation and Configuration
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S1D13504B00C Schematic Diagram 1 of 6
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Features
Configuration DIP Switch Settings
Installation and Configuration
Jumper Settings
Host Bus Selection
LCD / Ramdac Interface Pin Mapping
LCD Signal Connector J6
CPU / BUS Interface Connector Pinouts
CPU/BUS Connector H1 Pinout
Connector Comments Pin No
CPU/BUS Connector H2 Pinout
DB150 D150 D3116 WE1#
Host Bus Interface Pin Mapping
ISA Bus Support
Technical Description
Dram Support
Non-ISA Bus Support
Decode Logic
Clock Input Support
Color Passive LCD Panel Support
Monochrome LCD Panel Support
Color TFT LCD Panel Support
External Cmos Ramdac Support
Core VDD Power Supply
Power Save Modes
IO VDD Power Supply
Adjustable LCD Panel Negative Power Supply
15 CPU/Bus Interface Header Strips
Schematic Notes
Item # Qty/board Designation Part Value Description
Parts List
Texas Instrument PAL 24 pin DIP package/socketed
TIBPAL22V10-15BCNT
Diagrams
Schematic
S1D13504B00C Schematic Diagram 2
Rev.1.0
S1D13504B00C Schematic Diagram 4
Diagram 5
S1D13504B00C Schematic Diagram 6
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Document Number X19A-G-003-05
S5U13504-D9000
S5U13504-D9000 X19A-G-003-05 Issue Date 01/02/02
D9000 Specifics
Introduction Features
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S5U13504-D9000 Perspective View
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Reference
Display Buffer
S1D13504 Color Graphics LCD Controller
LCD Display Support
LCD Interface Pin Mapping
LCD Connector Pinout
CRT Support
Adjustable LCD Bias Power Supply
Connector Pinout for Channel A6 and A7
Interface Signals
Interface Signals
D9000 Specifics
Connector Pinout for Channel A7
GND
DC12V
Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ
Connectors Pinout for Channel A6
Channel A6 Pin # Fpga Signal S1D13504 Signal SmXY
BS# GND
Channel A6 Pin # Fpga Signal S1D13504 Signal SmZ
Bus Interface Timing
Board Dimensions
Memory Address CS#, M/R# Decode
Makefpga file
Item # Qty Reference Part Description
Parts List
Schematic
S5U13504-D9000 Schematic Diagram 2
S5U13504-D9000 Schematic Diagram 3
D9000
Component Placement
PCB Layout Component Placement
S5U13504-D9000 Perspective View
Perspective View
Document Number X19A-G-006-04
Power Consumption
S1D13504 Power Consumption X19A-G-006-04
S1D13504 Power Consumption
S1D13504 Total Power Consumption
Summary
Conditions
Document Number X19A-G-005-08
Interfacing to the Philips Mips PR31500/PR31700 Processor
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Direct Connection to the Philips PR31500/PR31700
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List of Tables
S1D13504 to PR31500/PR31700 Connection using One IT8368E
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Introduction
Interfacing to the PR31500/PR31700
S1D13504 Host Bus Interface
WAIT# RESET#
Generic MPU Host Bus Interface Pin Mapping
S1D13504 Generic MPU Pin Names
Generic MPU Host Bus Interface Signals
Hardware Description
Direct Connection to the Philips PR31500/PR31700
Memory Mapping and Aliasing
S1D13504 Configuration
MD1 MD2
MD3 MD4
Hardware Description-Using One IT8368E
System Design Using the IT8368E PC Card Buffer
Logic
Chip Select
Vancouver Design Center
PR31500/PR31700 S1D13504
Hardware Description-Using Two IT8368E’s
IT8368E Configuration
IT8368E Uses PC Card Slot # Philips Address Size Function
TX3912 Address Size Function CARDnIOEN=0 CARDnIOEN=1
S1D13504 Configuration using the IT8368E
Software
References
Documents
Document Sources
Epson LCD/CRT Controllers S1D13504
Technical Support
Philips Mips PR31500/PR31700 Processor
ITE IT8368E
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Document Number X19A-G-007-07
Interfacing to the NEC VR4102 Microprocessor
X19A-G-007-07 Issue Date 01/02/02
Introduction Interfacing to the NEC VR4102
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NEC VR4102 Read/Write Cycles
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Introduction
Interfacing to the NEC VR4102
NEC VR4102 System Bus
Overview
Lcdrdy
LCD Memory Access Cycles
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
VR4102 to S1D13504 Interface
Read/Write
Decode Logic
Generic bus interface e.g. MPC821, ISA bus interface
S1D13504 Hardware Configuration
NEC Signals Cycle S1D13504 Signals
NEC VR4102 Configuration
WR#
Write
Software
References
Japan North America Taiwan, R.O.C
NEC Electronics Inc. VR4102
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Interfacing to the Motorola MCF5307 Coldfire Microprocessor
X19A-G-011-07 Issue Date 01/02/02
S1D13504 Bus Interface
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List of Tables
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Introduction
Interfacing to the MCF5307
MCF5307 System Bus
Normal Non-Burst Bus Transactions
MCF5307 Memory Read Cycle
Burst Cycles
Chip-Select Module
S1D13504 Bus Interface
Generic MPU Host Bus Interface Signals
Hardware Connections
MCF5307 To S1D13504 Interface
S1D13504 Configuration Settings
Memory/Register Mapping
MCF5307 Chip Select Configuration
Software
Motorola Inc. Motorola Literature Distribution Center, 800
Motorola MCF5307 Processor
S1D13504 Color Graphics LCD / CRT Controller
X19A-G-013-02 Issue Date 01/02/02
Introduction Interfacing to the MC68328
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Generic MPU Host Bus Interface Pin Mapping
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Introduction
68328 System Bus
Interfacing to the MC68328
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
MC68328 To S1D13504 Interface
Busclk RESET#
CSB3 Dtack UWE LWE CLK0
MD7
MD6
Option Memory Selection
MC68328 Chip Select Configuration
Software
References
Motorola MC68328 Processor
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Interfacing to the Motorola MPC821 Microprocessor
X19A-G-010-05 Issue Date 01/02/02
Introduction Interfacing to the MPC821
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List of Tables
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Introduction
Interfacing to the MPC821
MPC8xx System Bus
MPC821 Bus Overview
Power PC Memory Read Cycle
Power PC Memory Write Cycle
General-Purpose Chip Select Module Gpcm
Memory Controller Module
User-Programmable Machine UPM
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Typical Implementation of MPC821 to S1D13504 Interface
MPC821 to S1D13504 Interface
AB8
AB9
AB7
AB6
Sysclk
Sreset
CS4
WE0
S1D13504 Hardware Configuration
Register/Memory Mapping
MPC821 Chip Select Configuration
Source Code
Test Software
Epson Research and Development
Software
References
Motorola MPC821 Processor
Document Number X19A-G-009-05
Interfacing to the PC Card Bus
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Introduction Interfacing to the PC Card Bus
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PC Card Read Cycle
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Introduction
Interfacing to the PC Card Bus
Memory Access Cycles
PC Card System Bus
PC Card Overview
PC Card Read Cycle
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Typical Implementation of PC Card to S1D13504 Interface
PC Card to S1D13504 Interface
Generic MPU
SH-3
Equations
PAL Equations
Software
PCMCIA/JEIDA, PC Card Standard -- March
Pcmcia
PC Card Standard
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Document Number X19A-G-012-04
Interfacing to the Toshiba Mips TX3912 Processor
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Direct Connection to the Toshiba TX3912
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S1D13504 to TX3912 Connection using One IT8368E
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Introduction
Interfacing to the TX3912
S1D13504 Host Bus Interface
Generic MPU Host Bus Interface Signals
Direct Connection to the Toshiba TX3912
Memory Mapping and Aliasing
S1D13504 Hardware Configuration
System Design Using the IT8368E PC Card Buffer
S1D13504 to TX3912 Connection using One IT8368E
Hardware Description-Using Two IT8368E’s
S1D13504 to TX3912 Connection using Two IT8368E
IT8368E Configuration
64Mb Card 2 Attribute
64Mb
64Mb Card 1 Memory
64Mb Card 2 Memory
S1D13504 Configuration
Software
References
Toshiba Mips TX3912 Processor ITE IT8368E
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