Epson S1D13504 - page 45

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Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
1. If the S1D13504 host interface is disabled, the timing for DTACK# driven high is relative to
the falling edge of AS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id,
whichever occurs later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become val-
id, whichever occurs later.
Table 7-2: MC68K Bus 1 Interface Timing
Symbol Parameter Min Max Units
t1 Clock period 30 ns
t2 Clock pulse width high 5ns
t3 Clock pulse width low 5ns
t4 A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and
either UDS#=0 or LDS# = 0 4ns
t5 A[20:1], M/R# hold from AS# 0ns
t6 CS# hold from AS# 0ns
t7 R/W# setup to before to either UDS#=0 or LDS# = 0 5ns
t8 R/W# hold from AS# 0ns
t91AS# = 0 and CS# = 0 to DTACK# driven high 1ns
t10 AS# high to DTACK# high impedance 15ns
t11 D[15:0] valid to second CLK where CS# = 0 AS# = 0, and either
UDS#=0 or LDS# = 0 (write cycle) 0ns
t12 D[15:0] hold from falling edge of DTACK# (write cycle) 0ns
t132Falling edge of UDS#=0 or LDS# = 0 to D[15:0] driven (read
cycle) 3ns
t14 D[15:0] valid to DTACK# falling edge (read cycle) 0ns
t15 UDS# and LDS# high to D[15:0] invalid/high impedance (read
cycle) 211ns
t16 AS# high setup to CLK 3ns