Epson S1D13504 manual Suspend Sequencing, Suspend Enable Sequence

Epson Research and Development	Page 31
Vancouver Design Center

All other bits should be masked into the register on a write. i.e. do a read, modify with mask, and write to set the bits.

5.4 Suspend Sequencing

Care must be taken when enabling Suspend Mode with respect to the external Power Supply used to provide the LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage.

Controlling the LCD Drive Power Supply can be done using the S1D13504 LCDPWR# output signal or by 'other' means. The following example assumes that the LCDPWR# pin is being used.

5.4.1 Suspend Enable Sequence

Enable Suspend (Software Suspend= REG[1A] bit 0=1) or (Hardware Suspend enabled by the SUSPEND# input pin (MA9=0)): LCDPWR# will go to its inactive state within one vertical frame, while maintaining the LCD interface signals for 128 Vertical Frames (with the exception of FPFRAME(#?) which goes inactive at the same time as LCDPWR#).

If 128 frames is not enough 'time' to allow the LCD Drive power supply to decay to 0V, LCDPWR# can be controlled manually using REG[1A] bit 3.

After the 128 frame delay, the various clock sources may be disabled (depending on the specific application and DRAM Refresh options). The actual 'time' for the 128 frame delay can be shortened by using the following example.

Shortening the 128 Frame delay using Software Suspend

1.Disable the Display FIFO: blank the screen.

2.Change the Horizontal and Vertical resolution to the minimum values allowed by the registers.

3.Enable Software Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced.

4.Restore the Horizontal and Vertical resolution registers to their original values.

5.Disable Software Suspend.

6.Enable the Display FIFO.

Shortening the 128 Frame Delay using Hardware SUSPEND#

Due to the fact that the registers can not be programmed in Hardware Suspend Mode, the following routine must be followed to shorten the delay:

1.Disable the Display FIFO: blank the screen.

2.Change the Horizontal and Vertical resolutions to the minimum values as allowed by the registers.

Programming Notes and Examples	S1D13504
Issue Date: 01/02/01	X19A-G-002-07