Epson S1D13504 Performance Enhancement Register, REG22h EDO Read RC Timing RAS# to, REG22h Bits

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Performance Enhancement Register 0

REG[22h]							RW
EDO Read-	RC Timing	RC Timing	RAS# to	RAS#	RAS#
				Precharge	Precharge	n/a	Reserved
Write Delay	Value Bit 1	Value Bit 0	CAS# Delay
				Timing Bit 1	Timing Bit 0

Note

Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see S1D13504 Programming Notes and Examples, document number X19A-G-002-xx.

bit 7	EDO Read-Write Delay
	This bit is used for EDO-DRAM to select the delay during the read-write transition. A “0” selects 2
	MCLK delay for the read-write transition. A “1” selects 1 MCLK delay for the read-write DRAM.
	This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transi-
	tion. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz.
bits 6-5	RC Timing Value (NRC) Bits [1:0]
	These bits select the DRAM random-cycle timing parameter, tRC. These bits specify the number
	(NRC) of MCLK periods (TM) used to create tRC. NRC should be chosen to meet tRC as well as
	tRAS, the RAS pulse width. Use the following two formulae to calculate NRC then choose the larger
	value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
	NRC	= Round-Up (tRC/TM)
	NRC	= Round-Up (tRAS/TM + NRP)	if NRP = 1 or 2
		= Round-Up (tRAS/TM + 1.55)	if NRP = 1.5

The resulting tRC is related to NRC as follows:

	tRC	= (NRC) TM
		Table 8-11: Minimum Memory Timing Selection
	REG[22h] Bits [6:5]		NRC		Minimum Random Cycle
					Width (tRC)
	00		5		5 TM
	01		4		4 TM
	10		3		3 TM
	11		Reserved		Reserved
bit 4	RAS# to CAS# Delay (NRCD)
	This bit selects the DRAM RAS# to CAS# delay parameter, tRCD. This bit specifies the number
	(NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS#
	access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
	NRCD	= Round-Up((tRAC+ 5)/TM - 1)		if EDO and NRP = 1 or 2
		= 2		if EDO and NRP = 1.5
		= Round-Up(tRAC/TM- 1)		if FPM and NRP = 1 or 2
		= Round-Up(tRAC/TM- 0.45)		if FPM and NRP = 1.5

S1D13504	Hardware Functional Specification
X19A-A-002-18	Issue Date: 01/01/30