Epson Programming the S1D13504 Registers, 2 REG22 bits 7-2 Performance Enhancement Register

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2 Programming the S1D13504 Registers

This section describes how to program the S1D13504 registers that require special consideration. It also provides the correct sequence for initializing the S1D13504 and disabling the half frame buffer.

For further information on the any of the registers described below, refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx.

2.1 Registers Requiring Special Consideration

2.1.1 REG[01] bit 0 - Memory Type

This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM Refresh will not cause any problems.

Note

This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see Register Initialization in Section 2.1.5).

2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0

This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM Refresh will not cause any problems.

Note

This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see Register Initialization in Section 2.1.5).

2.1.3 REG[02] bit 1 - Dual/Single Panel Type

This bit must not be changed while the Half Frame Buffer (HFB) is active.

Note

This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the HFB starts to R/W the memory (see Register Initialization in Section 2.1.5).

S1D13504	Programming Notes and Examples
X19A-G-002-07	Issue Date: 01/02/01