Epson S1D13504 manual Number of Pixels Panned Using Start Address, Active Pixel Pan Bits

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4.2.1 Registers

REG[10h] Screen 1 Display Start Address 0

Start Address	Start Address	Start Address	Start Address	Start Address	Start Address	Start Address	Start Address
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[11h] Screen 1 Display Start Address 1
Start Address	Start Address	Start Address	Start Address	Start Address	Start Address	Start Address	Start Address
Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8
REG[12h] Screen 1 Display Start Address 2
n/a	n/a	n/a	n/a	Start Address	Start Address	Start Address	Start Address
				Bit 19	Bit 18	Bit 17	Bit 16

These three registers form the address of the word in the display buffer where screen 1 will start displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on the current color depth. Refer to the following table to see the minimum number of pixels affected by a change of one to these registers.

Table 4-1: Number of Pixels Panned Using Start Address

Color Depth (bpp)	Pixels per Word	Number of Pixels Panned
1	16	16
2	8	8
4	4	4
8	2	2
15	1	1
16	1	1

REG[18h] Pixel Panning Register

Screen 2	Screen 2	Screen 2	Screen 2	Screen 1	Screen 1	Screen 1	Screen 1
Pixel Pan	Pixel Pan	Pixel Pan	Pixel Pan	Pixel Pan	Pixel Pan	Pixel Pan	Pixel Pan
Bit 3	Bit 2	Bit 1	Bit 0	Bit 3	Bit 2	Bit 1	Bit 0

The pixel panning register offers finer control over pixel pans than is available with the Start Address Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending on the current color depth certain bits of the pixel pan register are not used. The following table shows this.

Table 4-2: Active Pixel Pan Bits

Color Depth (bpp)	Pixel Pan bits used
1	bits [3:0]
2	bits [2:0]
4	bits [1:0]
8	bit 0
15/16	---

S1D13504	Programming Notes and Examples
X19A-G-002-07	Issue Date: 01/02/01