Epson Research and Development

Page 13

Vancouver Design Center

 

 

 

Table 3-2: Connector Pinout for Channel A7 (Continued)

Channel A7

Pin #

FPGA Signal

S1D13504 Signal

 

Pin #

FPGA Signal

S1D13504 Signal

 

 

 

 

 

 

 

4

chA7p4

N/C

 

24

GND

GND

 

 

 

 

 

 

 

5

chA7p5

N/C

 

25

dc3v

DC3V

6

chA7p6

N/C

 

26

GND

GND

 

 

 

 

 

 

 

7

chA7p7

N/C

 

27

dc3vs

N/C

8

chA7p8

N/C

 

28

GND

GND

 

 

 

 

 

 

 

9

chA7p9

N/C

 

29

dc12v

DC12V

10

chA7p10

N/C

 

30

GND

GND

 

 

 

 

 

 

 

11

ib1

N/C

 

31

battery

N/C

12

ib2

N/C

 

32

GND

GND

 

 

 

 

 

 

 

13

ib3

N/C

 

33

dcXA

N/C

14

ib4

N/C

 

34

base5vDc

N/C

 

 

 

 

 

 

 

15

ib5

N/C

 

35

dcXB

N/C

16

ib6

N/C

 

36

GND

GND

 

 

 

 

 

 

 

17

ib7

N/C

 

37

dcXC

N/C

18

ib8

N/C

 

38

GND

GND

 

 

 

 

 

 

 

19

GND

GND

 

39

senseH

N/C

20

GND

GND

 

40

senseL

N/C

 

 

 

 

 

 

 

Evaluation Board User Manual

S5U13504-D9000

Issue Date: 01/02/02

X19A-G-003-05

Page 345
Image 345
Epson S1D13504 manual Connector Pinout for Channel A7, Gnd, DC12V