Epson S1D13504 manual EDO Dram Read Timing

Page 48	Epson Research and Development
	Vancouver Design Center

Table 7-7: EDO DRAM Read Timing

Symbol	Parameter	Min	Typ	Max	Units
t1	Memory clock period	25			ns
	Random read or write cycle time (REG[22h] bits [6:5] = 00)	5 t1			ns
t2	Random read or write cycle time (REG[22h] bits [6:5] = 01)	4 t1			ns
	Random read or write cycle time (REG[22h] bits [6:5] = 10)	3 t1			ns
	Row address setup time (REG[22h] bits [3:2] = 00)	2.45 t1			ns
t3	Row address setup time (REG[22h] bits [3:2] = 01)	2 t1			ns
	Row address setup time (REG[22h] bits [3:2] = 10)	1.45 t1			ns
t4	Row address hold time (REG[22h] bits [3:2] = 00 or 10)	0.45 t1 - 1			ns
	Row address hold time (REG[22h] bits [3:2] = 01)	t1 - 1			ns
t5	Column address setup time	0.45 t1 - 1			ns
t6	Column address hold time	0.45 t1 - 1			ns
t7	CAS# pulse width	0.45 t1		0.55 t1 + 1	ns
t8	CAS# precharge time	0.45 t1 - 1		0.55 t1	ns
t9	RAS# hold time	1 t1			ns
	RAS# precharge time (REG[22h] bits [3:2] = 00)	2 t1 - 1			ns
t10	RAS# precharge time (REG[22h] bits [3:2] = 01)	1.45 t1 - 1			ns
	RAS# precharge time (REG[22h] bits [3:2] = 10)	1 t1 - 1			ns
	RAS# to CAS# delay time	2 t1 - 2		2 t1	ns
	(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t11
	RAS# to CAS# delay time	1 t1 - 2		1 t1	ns
	(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
	RAS# to CAS# delay time (REG[22h] bits [3:2] = 01)	1.45 t1 - 2		1.55 t1	ns
	Access time from RAS#			3 t1 - 11	ns
	(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t12	Access time from RAS#			2 t1 - 11	ns
	(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
	Access time from RAS# (REG[22h] bits [3:2] = 01)			2.45 t1 - 12	ns
t13	Access time from CAS#			t1 - 10	ns
t14	Access time from CAS# precharge, column address			1.45 t1 - 6	ns
t15	Read Data hold after CAS# low	2			ns
t16	Read Data turn-off delay from RAS#	2			ns

S1D13504	Hardware Functional Specification
X19A-A-002-18	Issue Date: 01/01/30